source: trunk/3DEES/classifier.v@ 181

Last change on this file since 181 was 181, checked in by demin, 11 years ago

working classifier
File size: 5.8 KB
Line 
1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [14*width-1:0] cfg_data,
8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
10 output wire [5:0] out_data,
11 output wire out_flag
12 );
13
14 reg out_flag_reg, out_flag_next;
15 reg [5:0] out_data_reg, out_data_next;
16 reg [5:0] inp_flag_reg, inp_flag_next;
17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
19 reg [1:0] int_data_reg [3:0], int_data_next [3:0];
20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
21
22 wire [width-1:0] inp_data_wire [5:0];
23 wire [3:0] int_pipe_wire [5:0];
24 wire [13:0] int_comp_wire;
25
26 integer i;
27 genvar j;
28
29 generate
30 for (j = 0; j < 6; j = j + 1)
31 begin : CLASSIFIER_INPUT_DATA
32 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
33 end
34 endgenerate
35
36 generate
37 assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]);
38 assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]);
39 for (j = 0; j < 4; j = j + 1)
40 begin : CLASSIFIER_COMPARTORS
41 assign int_comp_wire[j*3+0+2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);
42 assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
43 assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
44 end
45 endgenerate
46
47 generate
48 for (j = 0; j < 4; j = j + 1)
49 begin : CLASSIFIER_PIPELINE
50 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
51 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
52 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
53 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
54 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
55 assign int_pipe_wire[j+2][3] = 1'b0;
56 end
57 endgenerate
58
59 always @(posedge clock)
60 begin
61 if (reset)
62 begin
63 inp_flag_reg <= {(6){1'b0}};
64 out_data_reg <= {(6){1'b0}};
65 out_flag_reg <= 1'b0;
66 for (i = 0; i < 6; i = i + 1)
67 begin
68 inp_data_reg[i] <= {(width){1'b0}};
69 end
70 for (i = 0; i < 20; i = i + 1)
71 begin
72 int_pipe_reg[i] <= {(16){1'b0}};
73 end
74 for (i = 0; i < 4; i = i + 1)
75 begin
76 int_data_reg[i] <= {(2){1'b0}};
77 end
78 for (i = 0; i < 2; i = i + 1)
79 begin
80 int_temp_reg[i] <= {(5){1'b0}};
81 end
82 end
83 else
84 begin
85 inp_flag_reg <= inp_flag_next;
86 out_data_reg <= out_data_next;
87 out_flag_reg <= out_flag_next;
88 for (i = 0; i < 6; i = i + 1)
89 begin
90 inp_data_reg[i] <= inp_data_next[i];
91 end
92 for (i = 0; i < 20; i = i + 1)
93 begin
94 int_pipe_reg[i] <= int_pipe_next[i];
95 end
96 for (i = 0; i < 4; i = i + 1)
97 begin
98 int_data_reg[i] <= int_data_next[i];
99 end
100 for (i = 0; i < 2; i = i + 1)
101 begin
102 int_temp_reg[i] <= int_temp_next[i];
103 end
104 end
105 end
106
107 always @*
108 begin
109 inp_flag_next = inp_flag_reg;
110 out_data_next = out_data_reg;
111 out_flag_next = out_flag_reg;
112 for (i = 0; i < 6; i = i + 1)
113 begin
114 inp_data_next[i] = inp_data_reg[i];
115 end
116 for (i = 0; i < 20; i = i + 1)
117 begin
118 int_pipe_next[i] = int_pipe_reg[i];
119 end
120 for (i = 0; i < 4; i = i + 1)
121 begin
122 int_data_next[i] = int_data_reg[i];
123 end
124 for (i = 0; i < 2; i = i + 1)
125 begin
126 int_temp_next[i] = int_temp_reg[i];
127 end
128
129 if (frame)
130 begin
131 inp_flag_next = inp_flag;
132 for (i = 0; i < 6; i = i + 1)
133 begin
134 inp_data_next[i] = inp_data_wire[i];
135 end
136
137 if (out_flag_reg)
138 begin
139 out_flag_next = 1'b0;
140 for (i = 0; i < 20; i = i + 1)
141 begin
142 int_pipe_next[i] = {(16){1'b0}};
143 end
144 int_temp_next[0] = {(5){1'b0}};
145 int_temp_next[1] = {(5){1'b0}};
146 out_data_next = {(6){1'b0}};
147 end
148 else
149 begin
150 out_flag_next = 1'b1;
151 int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
152 int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
153 for (i = 2; i < 8; i = i + 1)
154 begin
155 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
156 end
157 for (i = 8; i < 20; i = i + 1)
158 begin
159 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
160 end
161
162 for (i = 0; i < 4; i = i + 1)
163 begin
164 case (int_pipe_wire[i+2][2:0])
165 3'b000: int_data_next[i] = 2'd0;
166 3'b001: int_data_next[i] = 2'd1;
167 3'b011: int_data_next[i] = 2'd2;
168 3'b111: int_data_next[i] = 2'd3;
169 default: int_data_next[i] = 2'd0;
170 endcase
171 end
172
173 int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]};
174 int_temp_next[1] = {1'b0, int_pipe_wire[0]};
175
176 case (int_temp_reg[0][4:0])
177 5'b00011: out_data_next[3:0] = {2'd0, int_data_next[0]};
178 5'b00111: out_data_next[3:0] = {2'd1, int_data_next[1]};
179 5'b01111: out_data_next[3:0] = {2'd2, int_data_next[2]};
180 5'b11111: out_data_next[3:0] = {2'd3, int_data_next[3]};
181 default: out_flag_next = 1'b0;
182 endcase
183
184 case (int_temp_reg[1][3:0])
185 // S1_F, electron
186 4'b0100: out_data_next[5:4] = 2'd0;
187
188 // S1_F, proton
189 4'b0101: out_data_next[5:4] = 2'd1;
190
191 // S1_S, electron
192 4'b1000: out_data_next[5:4] = 2'd2;
193
194 // S1_S, proton
195 4'b1010: out_data_next[5:4] = 2'd3;
196
197 default: out_flag_next = 1'b0;
198 endcase
199 end
200 end
201 end
202
203// assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
204// assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
205// assign out_data = {1'd0, int_temp_reg[0][4:0]};
206 assign out_data = out_data_reg;
207 assign out_flag = out_flag_reg;
208
209endmodule
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