source: trunk/3DEES/classifier.v@ 180

Last change on this file since 180 was 180, checked in by demin, 11 years ago

add classifier and remove unneeded modules
File size: 5.1 KB
Line 
1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [14*width-1:0] cfg_data,
8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
10 output wire [5:0] out_data,
11 output wire out_flag
12 );
13
14 reg int_case_reg, int_case_next;
15 reg out_flag_reg, out_flag_next;
16 reg [5:0] out_data_reg, out_data_next;
17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
19 reg [1:0] int_data_reg [3:0], int_data_next [3:0];
20
21 wire [width-1:0] inp_data_wire [5:0];
22 wire [3:0] int_pipe_wire [5:0];
23 wire [13:0] int_comp_wire;
24
25 integer i;
26 genvar j;
27
28 generate
29 for (j = 0; j < 6; j = j + 1)
30 begin : CLASSIFIER_INPUT_DATA
31 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
32 end
33 endgenerate
34
35 generate
36 assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]);
37 assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]);
38 for (j = 0; j < 4; j = j + 1)
39 begin : CLASSIFIER_COMPARTORS
40 assign int_comp_wire[j*3+0+2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);
41 assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
42 assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
43 end
44 endgenerate
45
46 generate
47 for (j = 0; j < 4; j = j + 1)
48 begin : CLASSIFIER_PIPELINE
49 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
50 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
51 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
52 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
53 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
54 assign int_pipe_wire[j+2][3] = 1'b0;
55 end
56 endgenerate
57
58 always @(posedge clock)
59 begin
60 if (reset)
61 begin
62 out_data_reg <= {(6){1'b0}};
63 out_flag_reg <= 1'b0;
64 for (i = 0; i < 6; i = i + 1)
65 begin
66 inp_data_reg[i] <= {(width){1'b0}};
67 end
68 for (i = 0; i < 20; i = i + 1)
69 begin
70 int_pipe_reg[i] <= {(16){1'b0}};
71 end
72 for (i = 0; i < 4; i = i + 1)
73 begin
74 int_data_reg[i] <= {(2){1'b0}};
75 end
76 end
77 else
78 begin
79 out_data_reg <= out_data_next;
80 out_flag_reg <= out_flag_next;
81 for (i = 0; i < 6; i = i + 1)
82 begin
83 inp_data_reg[i] <= inp_data_next[i];
84 end
85 for (i = 0; i < 20; i = i + 1)
86 begin
87 int_pipe_reg[i] <= int_pipe_next[i];
88 end
89 for (i = 0; i < 4; i = i + 1)
90 begin
91 int_data_reg[i] <= int_data_next[i];
92 end
93 end
94 end
95
96 always @*
97 begin
98 out_data_next = out_data_reg;
99 out_flag_next = out_flag_reg;
100 for (i = 0; i < 6; i = i + 1)
101 begin
102 inp_data_next[i] = inp_data_reg[i];
103 end
104 for (i = 0; i < 20; i = i + 1)
105 begin
106 int_pipe_next[i] = int_pipe_reg[i];
107 end
108 for (i = 0; i < 4; i = i + 1)
109 begin
110 int_data_next[i] = int_data_reg[i];
111 end
112
113 if (frame)
114 begin
115 for (i = 0; i < 6; i = i + 1)
116 begin
117 inp_data_next[i] = inp_flag[i] ? inp_data_wire[i] : {(width){1'b0}};
118 end
119
120 if (out_flag_reg)
121 begin
122 out_flag_next = 1'b0;
123 for (i = 0; i < 20; i = i + 1)
124 begin
125 int_pipe_next[i] = {(16){1'b0}};
126 end
127 out_data_next = {(6){1'b0}};
128 end
129 else
130 begin
131 out_flag_next = 1'b1;
132 int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
133 int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
134 for (i = 2; i < 8; i = i + 1)
135 begin
136 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag[i-2]};
137 end
138 for (i = 8; i < 20; i = i + 1)
139 begin
140 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
141 end
142
143 for (i = 0; i < 4; i = i + 1)
144 begin
145 case (int_pipe_wire[i+2][2:0])
146 3'b000: int_data_next[i] = 2'd0;
147 3'b001: int_data_next[i] = 2'd1;
148 3'b011: int_data_next[i] = 2'd2;
149 3'b111: int_data_next[i] = 2'd3;
150 default: int_data_next[i] = 2'd0;
151 endcase
152 end
153
154 case ({int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]})
155 5'b00011: out_data_next[3:0] = {2'd0, int_data_next[0]};
156 5'b00111: out_data_next[3:0] = {2'd1, int_data_next[1]};
157 5'b01111: out_data_next[3:0] = {2'd2, int_data_next[2]};
158 5'b11111: out_data_next[3:0] = {2'd3, int_data_next[3]};
159 default: out_flag_next = 1'b0;
160 endcase
161
162 case (int_pipe_wire[0])
163 // S1_F, electron
164 4'b0001: out_data_next[5:4] = 2'd0;
165
166 // S1_F, proton
167 4'b0101: out_data_next[5:4] = 2'd1;
168
169 // S1_S, electron
170 4'b0010: out_data_next[5:4] = 2'd2;
171
172 // S1_S, proton
173 4'b1010: out_data_next[5:4] = 2'd3;
174
175 default: out_flag_next = 1'b0;
176 endcase
177 end
178 end
179 end
180
181// assign out_data = {2'd0, int_data_reg[1]};
182// assign out_data = {2'd0, int_pipe_wire[7:4]};
183 assign out_data = out_data_reg;
184 assign out_flag = out_flag_reg;
185
186endmodule
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