Changeset 183 for trunk/3DEES/classifier.v
- Timestamp:
- Jan 24, 2014, 3:33:37 PM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/classifier.v
r181 r183 12 12 ); 13 13 14 reg out_flag_reg , out_flag_next;15 reg [5:0] out_data_reg , out_data_next;14 reg out_flag_reg [2:0], out_flag_next [2:0]; 15 reg [5:0] out_data_reg [2:0], out_data_next [2:0]; 16 16 reg [5:0] inp_flag_reg, inp_flag_next; 17 17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0]; 18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0]; 18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0]; 19 19 reg [1:0] int_data_reg [3:0], int_data_next [3:0]; 20 20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0]; … … 42 42 assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]); 43 43 assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]); 44 end 44 end 45 45 endgenerate 46 46 47 47 generate 48 48 for (j = 0; j < 4; j = j + 1) … … 56 56 end 57 57 endgenerate 58 58 59 59 always @(posedge clock) 60 60 begin … … 62 62 begin 63 63 inp_flag_reg <= {(6){1'b0}}; 64 out_data_reg <= {(6){1'b0}}; 65 out_flag_reg <= 1'b0; 64 for (i = 0; i < 3; i = i + 1) 65 begin 66 out_data_reg[i] <= {(6){1'b0}}; 67 out_flag_reg[i] <= 1'b0; 68 end 66 69 for (i = 0; i < 6; i = i + 1) 67 70 begin … … 84 87 begin 85 88 inp_flag_reg <= inp_flag_next; 86 out_data_reg <= out_data_next; 87 out_flag_reg <= out_flag_next; 89 for (i = 0; i < 3; i = i + 1) 90 begin 91 out_data_reg[i] <= out_data_next[i]; 92 out_flag_reg[i] <= out_flag_next[i]; 93 end 88 94 for (i = 0; i < 6; i = i + 1) 89 95 begin … … 104 110 end 105 111 end 106 112 107 113 always @* 108 114 begin 109 115 inp_flag_next = inp_flag_reg; 110 out_data_next = out_data_reg; 111 out_flag_next = out_flag_reg; 116 for (i = 0; i < 3; i = i + 1) 117 begin 118 out_data_next[i] = out_data_reg[i]; 119 out_flag_next[i] = out_flag_reg[i]; 120 end 112 121 for (i = 0; i < 6; i = i + 1) 113 122 begin … … 134 143 inp_data_next[i] = inp_data_wire[i]; 135 144 end 136 137 if (out_flag_reg) 138 begin 139 out_flag_next = 1'b0; 145 146 if (out_flag_reg[2]) 147 begin 148 for (i = 0; i < 3; i = i + 1) 149 begin 150 out_data_next[i] = {(6){1'b0}}; 151 out_flag_next[i] = 1'b0; 152 end 140 153 for (i = 0; i < 20; i = i + 1) 141 154 begin … … 144 157 int_temp_next[0] = {(5){1'b0}}; 145 158 int_temp_next[1] = {(5){1'b0}}; 146 out_data_next = {(6){1'b0}};147 159 end 148 160 else 149 161 begin 150 out_flag_next = 1'b1; 162 out_data_next[0] = {(6){1'b0}}; 163 out_data_next[1] = out_data_reg[0]; 164 out_data_next[2] = out_data_reg[1]; 165 166 out_flag_next[0] = 1'b1; 167 out_flag_next[1] = out_flag_reg[0]; 168 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]); 169 151 170 int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]}; 152 171 int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]}; … … 170 189 endcase 171 190 end 172 191 173 192 int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]}; 174 193 int_temp_next[1] = {1'b0, int_pipe_wire[0]}; 175 194 176 195 case (int_temp_reg[0][4:0]) 177 5'b00011: out_data_next[ 3:0] = {2'd0, int_data_next[0]};178 5'b00111: out_data_next[ 3:0] = {2'd1, int_data_next[1]};179 5'b01111: out_data_next[ 3:0] = {2'd2, int_data_next[2]};180 5'b11111: out_data_next[ 3:0] = {2'd3, int_data_next[3]};181 default: out_flag_next = 1'b0;196 5'b00011: out_data_next[0][3:0] = {2'd0, int_data_next[0]}; 197 5'b00111: out_data_next[0][3:0] = {2'd1, int_data_next[1]}; 198 5'b01111: out_data_next[0][3:0] = {2'd2, int_data_next[2]}; 199 5'b11111: out_data_next[0][3:0] = {2'd3, int_data_next[3]}; 200 default: out_flag_next[0] = 1'b0; 182 201 endcase 183 202 184 203 case (int_temp_reg[1][3:0]) 185 204 // S1_F, electron 186 4'b0100: out_data_next[ 5:4] = 2'd0;187 205 4'b0100: out_data_next[0][5:4] = 2'd0; 206 188 207 // S1_F, proton 189 4'b0101: out_data_next[ 5:4] = 2'd1;190 208 4'b0101: out_data_next[0][5:4] = 2'd1; 209 191 210 // S1_S, electron 192 4'b1000: out_data_next[ 5:4] = 2'd2;193 211 4'b1000: out_data_next[0][5:4] = 2'd2; 212 194 213 // S1_S, proton 195 4'b1010: out_data_next[ 5:4] = 2'd3;196 197 default: out_flag_next = 1'b0;214 4'b1010: out_data_next[0][5:4] = 2'd3; 215 216 default: out_flag_next[0] = 1'b0; 198 217 endcase 199 218 end … … 204 223 // assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]}; 205 224 // assign out_data = {1'd0, int_temp_reg[0][4:0]}; 206 assign out_data = out_data_reg ;207 assign out_flag = out_flag_reg ;225 assign out_data = out_data_reg[2]; 226 assign out_flag = out_flag_reg[2]; 208 227 209 228 endmodule
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