Changeset 186 for trunk/3DEES/classifier.v
- Timestamp:
- Mar 18, 2014, 3:10:11 PM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/classifier.v (modified) (13 diffs)
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trunk/3DEES/classifier.v
r184 r186 5 5 ( 6 6 input wire clock, frame, reset, 7 input wire [ 18*width-1:0] cfg_data,7 input wire [22*width-1:0] cfg_data, 8 8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F} 9 9 input wire [5:0] inp_flag, 10 output wire [ 6:0] out_data,10 output wire [7:0] out_data, 11 11 output wire out_flag 12 12 ); 13 13 14 14 reg out_flag_reg [2:0], out_flag_next [2:0]; 15 reg [ 6:0] out_data_reg [2:0], out_data_next [2:0];15 reg [7:0] out_data_reg [2:0], out_data_next [2:0]; 16 16 reg [5:0] inp_flag_reg, inp_flag_next; 17 17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0]; 18 reg [15:0] int_pipe_reg [ 19:0], int_pipe_next [19:0];19 reg [ 1:0] int_data_reg [3:0], int_data_next [3:0];18 reg [15:0] int_pipe_reg [23:0], int_pipe_next [23:0]; 19 reg [2:0] int_data_reg [3:0], int_data_next [3:0]; 20 20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0]; 21 21 22 22 wire [width-1:0] inp_data_wire [5:0]; 23 23 wire [3:0] int_pipe_wire [5:0]; 24 wire [1 5:0] int_comp_wire;24 wire [19:0] int_comp_wire; 25 25 26 26 integer i; … … 43 43 for (j = 0; j < 4; j = j + 1) 44 44 begin : CLASSIFIER_COMPARTORS 45 assign int_comp_wire[j*3+0+4] = (inp_data_reg[j+2] > cfg_data[(j*3+0+6)*width+width-1:(j*3+0+6)*width]); 46 assign int_comp_wire[j*3+1+4] = (inp_data_reg[j+2] > cfg_data[(j*3+1+6)*width+width-1:(j*3+1+6)*width]); 47 assign int_comp_wire[j*3+2+4] = (inp_data_reg[j+2] > cfg_data[(j*3+2+6)*width+width-1:(j*3+2+6)*width]); 45 assign int_comp_wire[j*4+0+4] = (inp_data_reg[j+2] > cfg_data[(j*4+0+6)*width+width-1:(j*4+0+6)*width]); 46 assign int_comp_wire[j*4+1+4] = (inp_data_reg[j+2] > cfg_data[(j*4+1+6)*width+width-1:(j*4+1+6)*width]); 47 assign int_comp_wire[j*4+2+4] = (inp_data_reg[j+2] > cfg_data[(j*4+2+6)*width+width-1:(j*4+2+6)*width]); 48 assign int_comp_wire[j*4+3+4] = (inp_data_reg[j+2] > cfg_data[(j*4+3+6)*width+width-1:(j*4+3+6)*width]); 48 49 end 49 50 endgenerate … … 54 55 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]); 55 56 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]); 56 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j* 3+0+8]);57 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j* 3+1+8]);58 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j* 3+2+8]);59 assign int_pipe_wire[j+2][3] = 1'b0;57 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*4+0+8]); 58 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*4+1+8]); 59 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*4+2+8]); 60 assign int_pipe_wire[j+2][3] = (|int_pipe_reg[j*4+3+8]); 60 61 end 61 62 endgenerate … … 68 69 for (i = 0; i < 3; i = i + 1) 69 70 begin 70 out_data_reg[i] <= {( 6){1'b0}};71 out_data_reg[i] <= {(7){1'b0}}; 71 72 out_flag_reg[i] <= 1'b0; 72 73 end … … 75 76 inp_data_reg[i] <= {(width){1'b0}}; 76 77 end 77 for (i = 0; i < 2 0; i = i + 1)78 for (i = 0; i < 24; i = i + 1) 78 79 begin 79 80 int_pipe_reg[i] <= {(16){1'b0}}; … … 81 82 for (i = 0; i < 4; i = i + 1) 82 83 begin 83 int_data_reg[i] <= {( 2){1'b0}};84 int_data_reg[i] <= {(3){1'b0}}; 84 85 end 85 86 for (i = 0; i < 2; i = i + 1) … … 100 101 inp_data_reg[i] <= inp_data_next[i]; 101 102 end 102 for (i = 0; i < 2 0; i = i + 1)103 for (i = 0; i < 24; i = i + 1) 103 104 begin 104 105 int_pipe_reg[i] <= int_pipe_next[i]; … … 127 128 inp_data_next[i] = inp_data_reg[i]; 128 129 end 129 for (i = 0; i < 2 0; i = i + 1)130 for (i = 0; i < 24; i = i + 1) 130 131 begin 131 132 int_pipe_next[i] = int_pipe_reg[i]; … … 152 153 for (i = 0; i < 3; i = i + 1) 153 154 begin 154 out_data_next[i] = {( 6){1'b0}};155 out_data_next[i] = {(7){1'b0}}; 155 156 out_flag_next[i] = 1'b0; 156 157 end 157 for (i = 0; i < 2 0; i = i + 1)158 for (i = 0; i < 24; i = i + 1) 158 159 begin 159 160 int_pipe_next[i] = {(16){1'b0}}; … … 164 165 else 165 166 begin 166 out_data_next[0] = {( 6){1'b0}};167 out_data_next[0] = {(7){1'b0}}; 167 168 out_data_next[1] = out_data_reg[0]; 168 169 out_data_next[2] = out_data_reg[1]; … … 172 173 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]); 173 174 175 for (i = 0; i < 5; i = i + 1) 176 begin 177 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 178 end 179 for (i = 4; i < 8; i = i + 1) 180 begin 181 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]}; 182 end 183 for (i = 8; i < 24; i = i + 1) 184 begin 185 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]}; 186 end 187 174 188 for (i = 0; i < 4; i = i + 1) 175 189 begin 176 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 177 end 178 for (i = 4; i < 8; i = i + 1) 179 begin 180 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]}; 181 end 182 for (i = 8; i < 20; i = i + 1) 183 begin 184 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]}; 185 end 186 187 for (i = 0; i < 4; i = i + 1) 188 begin 189 case (int_pipe_wire[i+2][2:0]) 190 3'b000: int_data_next[i] = 2'b00; 191 3'b001: int_data_next[i] = 2'b01; 192 3'b011: int_data_next[i] = 2'b10; 193 3'b111: int_data_next[i] = 2'b11; 194 default: int_data_next[i] = 2'd0; 190 case (int_pipe_wire[i+2][3:0]) 191 4'b0000: int_data_next[i] = 3'b000; 192 4'b0001: int_data_next[i] = 3'b001; 193 4'b0011: int_data_next[i] = 3'b010; 194 4'b0111: int_data_next[i] = 3'b011; 195 4'b1111: int_data_next[i] = 3'b100; 196 default: int_data_next[i] = 3'b000; 195 197 endcase 196 198 end … … 200 202 201 203 case (int_temp_reg[0][4:0]) 202 5'b00011: out_data_next[0][ 3:0] = {2'b00, int_data_next[0]};203 5'b00111: out_data_next[0][ 3:0] = {2'b01, int_data_next[1]};204 5'b01111: out_data_next[0][ 3:0] = {2'b10, int_data_next[2]};205 5'b11111: out_data_next[0][ 3:0] = {2'b11, int_data_next[3]};204 5'b00011: out_data_next[0][4:0] = int_data_next[0]; 205 5'b00111: out_data_next[0][4:0] = int_data_next[1] + 4'd5; 206 5'b01111: out_data_next[0][4:0] = int_data_next[2] + 4'd10; 207 5'b11111: out_data_next[0][4:0] = int_data_next[3] + 4'd15; 206 208 default: out_flag_next[0] = 1'b0; 207 209 endcase … … 209 211 case (int_temp_reg[1][3:0]) 210 212 // S1_F, electron 211 4'b0001: out_data_next[0][ 6:4] = 3'b100;213 4'b0001: out_data_next[0][7:5] = 3'b100; 212 214 213 215 // S1_F, proton 214 4'b0010: out_data_next[0][ 6:4] = 3'b101;216 4'b0010: out_data_next[0][7:5] = 3'b101; 215 217 216 218 // S1_S, electron 217 4'b0100: out_data_next[0][ 6:4] = 3'b110;219 4'b0100: out_data_next[0][7:5] = 3'b110; 218 220 219 221 // S1_S, proton 220 4'b1000: out_data_next[0][ 6:4] = 3'b111;222 4'b1000: out_data_next[0][7:5] = 3'b111; 221 223 222 224 default: out_flag_next[0] = 1'b0;
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