| Rev | Line | |
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| [10] | 1 | module Paella
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| 2 | (
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| 3 | input wire CLK_50MHz,
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| [11] | 4 | output wire LED,
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| 5 |
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| 6 | inout wire [3:0] TRG,
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| 7 | inout wire [6:0] CON_A,
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| [22] | 8 | inout wire [15:0] CON_B,
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| [17] | 9 | inout wire [12:0] CON_C,
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| [11] | 10 | input wire [1:0] CON_BCLK,
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| 11 | input wire [1:0] CON_CCLK,
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| 12 |
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| 13 | input wire ADC_DCO,
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| 14 | input wire ADC_FCO,
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| 15 | input wire ADC_DB,
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| 16 | input wire ADC_DC,
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| 17 | input wire ADC_DD,
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| 18 |
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| [13] | 19 | output wire USB_SLRD,
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| 20 | output wire USB_SLWR,
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| 21 | input wire USB_IFCLK,
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| 22 | input wire USB_FLAGA,
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| 23 | input wire USB_FLAGB,
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| [11] | 24 | input wire USB_FLAGC,
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| 25 | inout wire [7:0] USB_PA,
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| 26 | inout wire [7:0] USB_PB,
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| 27 |
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| [13] | 28 | output wire RAM_CLK,
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| 29 | output wire RAM_CE1,
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| 30 | output wire RAM_WE,
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| [11] | 31 | output wire [19:0] RAM_ADDR,
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| 32 | inout wire RAM_DQAP,
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| 33 | inout wire [7:0] RAM_DQA,
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| 34 | inout wire RAM_DQBP,
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| 35 | inout wire [7:0] RAM_DQB
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| [10] | 36 | );
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| [22] | 37 |
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| [13] | 38 | // Turn off all output ports
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| 39 | assign USB_SLRD = 1'b0;
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| 40 | assign USB_SLWR = 1'b0;
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| 41 | assign RAM_CLK = 1'b0;
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| 42 | assign RAM_CE1 = 1'b0;
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| 43 | assign RAM_WE = 1'b0;
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| [15] | 44 | assign RAM_ADDR = 20'h00000;
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| [13] | 45 |
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| 46 | // All inout ports turn to tri-state
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| 47 | assign TRG = 4'bz;
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| 48 | assign CON_A = 7'bz;
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| 49 | assign CON_B = 17'bz;
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| [18] | 50 | assign CON_C = 13'bz;
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| [13] | 51 | assign USB_PA = 8'bz;
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| 52 | assign USB_PB = 8'bz;
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| 53 | assign RAM_DQAP = 1'bz;
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| 54 | assign RAM_DQA = 8'bz;
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| 55 | assign RAM_DQBP = 1'bz;
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| 56 | assign RAM_DQB = 8'bz;
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| 57 |
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| [10] | 58 | reg [31:0] counter;
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| 59 |
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| [13] | 60 | assign LED = counter[25];
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| [10] | 61 |
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| 62 | always @ (posedge CLK_50MHz)
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| 63 | begin
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| 64 | counter <= counter + 32'd1;
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| 65 | end
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| 66 |
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| 67 | endmodule
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