source: trunk/MultiChannelUSB/Paella.v@ 44

Last change on this file since 44 was 44, checked in by demin, 15 years ago

add baseline subtraction
File size: 10.7 KB
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[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
[30]54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
[27]58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
[30]63
64 assign USB_PA2 = ~usb_rden;
65 assign USB_PA4 = usb_addr[0];
66 assign USB_PA5 = usb_addr[1];
67 assign USB_PA6 = ~usb_pktend;
68
[27]69 reg [31:0] counter;
[31]70 reg led_reg;
[30]71// assign LED = counter[24];
[31]72 assign LED = led_reg;
[27]73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]75 wire usb_fifo_aclr;
[30]76 reg usb_fifo_tx_wrreq;
77 reg usb_fifo_rx_rdreq;
[27]78 wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]79 reg [7:0] usb_fifo_tx_data;
80 wire [7:0] usb_fifo_rx_data;
[27]81 wire [1:0] usb_addr;
82
83 assign USB_SLRD = ~usb_rdreq;
84 assign USB_SLWR = ~usb_wrreq;
85
86 usb_fifo usb_fifo_unit
87 (
88 .usb_clk(USB_IFCLK),
89 .usb_data(USB_PB),
90 .usb_full(~USB_FLAGB),
91 .usb_empty(~USB_FLAGA),
92 .usb_wrreq(usb_wrreq),
93 .usb_rdreq(usb_rdreq),
94 .usb_rden(usb_rden),
95 .usb_pktend(usb_pktend),
96 .usb_addr(usb_addr),
[34]97
[27]98 .clk(CLK_50MHz),
99 .aclr(usb_fifo_aclr),
[34]100
101 .tx_full(usb_fifo_tx_full),
102 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]103 .tx_data(usb_fifo_tx_data),
[34]104
[27]105 .rx_empty(usb_fifo_rx_empty),
[37]106 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]107 .rx_q(usb_fifo_rx_data)
[27]108 );
109
[37]110 reg [23:0] rx_counter;
[35]111 reg [10:0] tst_counter;
112
[44]113 reg ana_reset [2:0];
114 wire ana_peak_ready [2:0];
115 wire [11:0] ana_peak [2:0];
116
[35]117 reg [9:0] osc_counter;
[30]118 reg osc_byte_num;
[27]119
[44]120 reg osc_reset_mux, osc_reset [2:0];
121 wire [9:0] osc_start_addr [2:0];
122 reg [9:0] osc_start_addr_mux, osc_addr_mux, osc_addr [2:0];
123 wire [15:0] osc_q [2:0];
124 reg [15:0] osc_q_mux;
125
[30]126 reg [1:0] hst_byte_num;
[27]127
[44]128 reg hst_reset_mux, hst_reset [2:0];
129 reg [11:0] hst_addr_mux, hst_addr [2:0];
130 wire [31:0] hst_q [2:0];
131 reg [31:0] hst_q_mux;
132
133 reg [3:0] select, state1, state2;
[27]134 reg adc_fifo_aclr;
135
136 wire adc_clk;
[41]137
[27]138 reg [11:0] adc_data;
[41]139
[44]140 wire adc_data_ready [2:0];
[41]141 wire [11:0] adc_lvds_data [2:0];
142
[44]143 wire [11:0] raw_data [2:0];
144 wire [11:0] uwt_data [2:0];
145 wire [1:0] uwt_flag [2:0];
[27]146
147 pll pll_unit(
148 .inclk0(CLK_50MHz),
149 .c0(adc_clk));
[41]150/*
[38]151 altserial_flash_loader #(
152 .enable_shared_access("OFF"),
153 .enhanced_mode(1),
154 .intended_device_family("Cyclone III")) sfl_unit (
155 .noe(1'b0),
156 .asmi_access_granted(),
157 .asmi_access_request(),
158 .data0out(),
159 .dclkin(),
160 .scein(),
161 .sdoin());
[41]162*/
163 adc_lvds adc_lvds_unit (
164 .lvds_dco(ADC_DCO),
165 .lvds_fco(ADC_FCO),
166 .lvds_d(ADC_D),
167 .adc_db(adc_lvds_data[0]),
168 .adc_dc(adc_lvds_data[1]),
169 .adc_dd(adc_lvds_data[2]));
[44]170
171 genvar i;
172 generate
173 for (i = 0; i < 3; i = i + 1)
174 begin : MCA_CHAIN
175 adc_fifo adc_fifo_unit (
176 .adc_clk(ADC_FCO),
177 .adc_data(adc_lvds_data[i]),
178 .aclr(adc_fifo_aclr),
179 .rdclk(CLK_50MHz),
180 .ready(adc_data_ready[i]),
181 .raw_data(raw_data[i]),
182 .uwt_data({uwt_flag[i], uwt_data[i]}));
[27]183
[44]184 analyser analyser_unit (
185 .clk(CLK_50MHz),
186 .reset(ana_reset[i]),
187 .data_ready(adc_data_ready[i]),
188 .uwt_flag(uwt_flag[i]),
189 .uwt_data(uwt_data[i]),
190 .peak_ready(ana_peak_ready[i]),
191 .peak(ana_peak[i]));
192/*
193 histogram histogram_unit (
194 .clk(CLK_50MHz),
195 .reset(hst_reset[i]),
196 .data_ready(adc_data_ready[i]),
197 .data(raw_data[i]),
198 .address(hst_addr[i]),
199 .q(hst_q[i]));
200*/
201 histogram histogram_unit (
202 .clk(CLK_50MHz),
203 .reset(hst_reset[i]),
204 .data_ready(ana_peak_ready[i]),
205 .data(ana_peak[i]),
206 .address(hst_addr[i]),
207 .q(hst_q[i]));
208
209 oscilloscope oscilloscope_unit (
210 .clk(CLK_50MHz),
211 .reset(osc_reset[i]),
212 .data_ready(adc_data_ready[i]),
213 .raw_data(raw_data[i]),
214 .uwt_data(uwt_data[i]),
215 .threshold(16'd100),
216 .address(osc_addr[i]),
217 .start_address(osc_start_addr[i]),
218 .q(osc_q[i]));
219 end
220 endgenerate
[27]221
[30]222/*
[27]223 always @ (posedge adc_clk)
224 begin
225 counter <= counter + 32'd1;
226 end
[30]227*/
[27]228
[44]229 always @*
[27]230 begin
[44]231 case(select)
232 4'h0:
[27]233 begin
[44]234 osc_reset[0] = osc_reset_mux;
235 osc_addr[0] = osc_addr_mux;
236 osc_q_mux = osc_q[0];
237 osc_start_addr_mux = osc_start_addr[0];
238
239 hst_reset[0] = hst_reset_mux;
240 hst_addr[0] = hst_addr_mux;
241 hst_q_mux = hst_q[0];
[27]242 end
[44]243 4'h1:
[27]244 begin
[44]245 osc_reset[1] = osc_reset_mux;
246 osc_addr[1] = osc_addr_mux;
247 osc_q_mux = osc_q[1];
248 osc_start_addr_mux = osc_start_addr[1];
249
250 hst_reset[1] = hst_reset_mux;
251 hst_addr[1] = hst_addr_mux;
252 hst_q_mux = hst_q[1];
[27]253 end
[44]254 4'h2:
255 begin
256 osc_reset[2] = osc_reset_mux;
257 osc_addr[2] = osc_addr_mux;
258 osc_q_mux = osc_q[2];
259 osc_start_addr_mux = osc_start_addr[2];
260
261 hst_reset[2] = hst_reset_mux;
262 hst_addr[2] = hst_addr_mux;
263 hst_q_mux = hst_q[2];
264 end
[27]265 default:
266 begin
[44]267 osc_reset[0] = osc_reset_mux;
268 osc_addr[0] = osc_addr_mux;
269 osc_q_mux = osc_q[0];
270 osc_start_addr_mux = osc_start_addr[0];
271
272 hst_reset[0] = hst_reset_mux;
273 hst_addr[0] = hst_addr_mux;
274 hst_q_mux = hst_q[0];
[27]275 end
276 endcase
277 end
[35]278
[30]279 always @(posedge CLK_50MHz)
280 begin
[37]281 if (~usb_fifo_rx_empty)
282 begin
283 led_reg <= 1'b0;
284 rx_counter <= 24'd0;
285 end
286 else
287 begin
288 if (&rx_counter)
289 begin
290 led_reg <= 1'b1;
291 end
292 else
293 begin
294 rx_counter <= rx_counter + 24'd1;
295 end
296 end
297
[35]298 case(state1)
[30]299 1:
300 begin
[37]301 usb_fifo_rx_rdreq <= 1'b1;
[30]302 usb_fifo_tx_wrreq <= 1'b0;
[44]303 hst_reset_mux <= 1'b0;
304 osc_reset_mux <= 1'b0;
[35]305 state1 <= 4'd2;
[30]306 end
307
308 2:
309 begin
310 if (~usb_fifo_rx_empty)
311 begin
312 case (usb_fifo_rx_data)
[44]313 8'h40, 8'h41, 8'h42:
[30]314 begin
[37]315 usb_fifo_rx_rdreq <= 1'b0;
[44]316 hst_reset_mux <= 1'b1;
317 select <= usb_fifo_rx_data[3:0];
[35]318 state1 <= 4'd1;
[30]319 end
[44]320 8'h50, 8'h51, 8'h52:
[30]321 begin
[37]322 usb_fifo_rx_rdreq <= 1'b0;
[44]323 hst_addr_mux <= 12'd0;
[30]324 hst_byte_num <= 2'd0;
[44]325 select <= usb_fifo_rx_data[3:0];
[35]326 state1 <= 4'd3;
[30]327 end
[44]328 8'h60, 8'h61, 8'h62:
[30]329 begin
[37]330 usb_fifo_rx_rdreq <= 1'b0;
[44]331 osc_reset_mux <= 1'b1;
332 select <= usb_fifo_rx_data[3:0];
[35]333 state1 <= 4'd1;
[30]334 end
[44]335 8'h70, 8'h71, 8'h72:
[30]336 begin
[37]337 usb_fifo_rx_rdreq <= 1'b0;
[44]338 osc_addr_mux <= osc_start_addr_mux;
[30]339 osc_counter <= 10'd0;
340 osc_byte_num <= 1'd0;
[44]341 select <= usb_fifo_rx_data[3:0];
[35]342 state1 <= 4'd6;
[30]343 end
[44]344 8'h30:
[35]345 begin
[37]346 usb_fifo_rx_rdreq <= 1'b0;
[35]347 state1 <= 4'd1;
348 end
[44]349 8'h31:
[35]350 begin
[37]351 usb_fifo_rx_rdreq <= 1'b0;
[35]352 tst_counter <= 11'd0;
353 state1 <= 4'd9;
354 end
[30]355 endcase
356 end
357 end
358
[35]359 // hst transfer
[30]360 3:
361 begin
[44]362 usb_fifo_tx_data <= hst_q_mux[7:0];
[35]363 usb_fifo_tx_wrreq <= 1'b1;
364 hst_byte_num <= 2'd1;
365 state1 <= 4'd4;
366 end
367 4:
368 begin
[30]369 if (~usb_fifo_tx_full)
370 begin
371 case (hst_byte_num)
[44]372 2'd0: usb_fifo_tx_data <= hst_q_mux[7:0];
373 2'd1: usb_fifo_tx_data <= hst_q_mux[15:8];
374 2'd2: usb_fifo_tx_data <= hst_q_mux[23:16];
375 2'd3: usb_fifo_tx_data <= hst_q_mux[31:24];
[30]376 endcase
[44]377 if ((&hst_byte_num) & (&hst_addr_mux))
[30]378 begin
[35]379 state1 <= 4'd5;
[30]380 end
[35]381 else
[34]382 begin
[35]383 if (&hst_byte_num)
384 begin
[44]385 hst_addr_mux <= hst_addr_mux + 12'd1;
[35]386 end
387 hst_byte_num <= hst_byte_num + 2'd1;
[34]388 end
[30]389 end
390 end
[34]391 5:
392 begin
393 if (~usb_fifo_tx_full)
394 begin
[35]395 usb_fifo_tx_wrreq <= 1'b0;
396 state1 <= 4'd1;
[34]397 end
398 end
399
[35]400 // osc transfer
[34]401 6:
402 begin
[44]403 usb_fifo_tx_data <= osc_q_mux[7:0];
[35]404 usb_fifo_tx_wrreq <= 1'b1;
405 osc_byte_num <= 1'd1;
406 state1 <= 4'd7;
[34]407 end
[35]408 7:
[34]409 begin
[35]410 if (~usb_fifo_tx_full)
[30]411 begin
412 case (osc_byte_num)
[44]413 1'd0: usb_fifo_tx_data <= osc_q_mux[7:0];
414 1'd1: usb_fifo_tx_data <= osc_q_mux[15:8];
[30]415 endcase
[35]416 if ((&osc_byte_num) & (&osc_counter))
[30]417 begin
[35]418 state1 <= 4'd8;
[30]419 end
[35]420 else
[34]421 begin
[35]422 if (&osc_byte_num)
423 begin
[44]424 osc_addr_mux <= osc_addr_mux + 10'd1;
[35]425 osc_counter <= osc_counter + 10'd1;
426 end
427 osc_byte_num <= osc_byte_num + 1'd1;
[34]428 end
[30]429 end
430 end
[35]431 8:
[30]432 begin
[35]433 if (~usb_fifo_tx_full)
[30]434 begin
[35]435 usb_fifo_tx_wrreq <= 1'b0;
436 state1 <= 4'd1;
[30]437 end
[34]438 end
[35]439 // tst transfer
440 9:
[34]441 begin
[35]442 usb_fifo_tx_data <= tst_counter;
[34]443 usb_fifo_tx_wrreq <= 1'b1;
[35]444 tst_counter <= tst_counter + 11'd1;
445 state1 <= 4'd10;
[34]446 end
[35]447 10:
[34]448 begin
449 if (~usb_fifo_tx_full)
[30]450 begin
[35]451 usb_fifo_tx_data <= tst_counter;
452 if (tst_counter == 11'd0) //(&osc_counter)
[34]453 begin
[35]454 state1 <= 4'd11;
[34]455 end
456 else
457 begin
[35]458 tst_counter <= tst_counter + 11'd1;
[34]459 end
[30]460 end
461 end
[35]462 11:
[30]463 begin
[34]464 if (~usb_fifo_tx_full)
[30]465 begin
[34]466 usb_fifo_tx_wrreq <= 1'b0;
[35]467 state1 <= 4'd1;
[30]468 end
469 end
[35]470
471 default:
472 begin
473 state1 <= 4'd1;
474 end
[30]475 endcase
476 end
[34]477
[27]478 always @ (posedge adc_clk)
479 begin
480 case (state2)
481 1:
482 begin
483 adc_data <= 12'd0;
[35]484 state2 <= 4'd2;
[27]485 end
486
487 2:
488 begin
489 adc_data <= 12'd1024;
[35]490 state2 <= 4'd3;
[27]491 end
492
493 3:
494 begin
495 adc_data <= 12'd2048;
[35]496 state2 <= 4'd4;
[27]497 end
498
499 4:
500 begin
501 adc_data <= 12'd3072;
[35]502 state2 <= 4'd5;
[27]503 end
504
505 5:
506 begin
507 adc_data <= 12'd4095;
[35]508 state2 <= 4'd1;
[27]509 end
510
511 default:
512 begin
[35]513 state2 <= 4'd1;
[27]514 end
515 endcase
516 end
517
518endmodule
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