[27] | 1 | module Paella
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| 2 | (
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| 3 | input wire CLK_50MHz,
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| 4 | output wire LED,
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| 5 |
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| 6 | inout wire [3:0] TRG,
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| 7 | inout wire [6:0] CON_A,
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| 8 | inout wire [15:0] CON_B,
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| 9 | inout wire [12:0] CON_C,
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| 10 | input wire [1:0] CON_BCLK,
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| 11 | input wire [1:0] CON_CCLK,
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| 12 |
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| 13 | input wire ADC_DCO,
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| 14 | input wire ADC_FCO,
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| 15 | input wire ADC_DB,
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| 16 | input wire ADC_DC,
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| 17 | input wire ADC_DD,
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| 18 |
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| 19 | output wire USB_SLRD,
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| 20 | output wire USB_SLWR,
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| 21 | input wire USB_IFCLK,
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| 22 | input wire USB_FLAGA, // EMPTY flag for EP6
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| 23 | input wire USB_FLAGB, // FULL flag for EP8
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| 24 | input wire USB_FLAGC,
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[30] | 25 | inout wire USB_PA0,
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| 26 | inout wire USB_PA1,
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| 27 | output wire USB_PA2,
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| 28 | inout wire USB_PA3,
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| 29 | output wire USB_PA4,
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| 30 | output wire USB_PA5,
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| 31 | output wire USB_PA6,
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| 32 | inout wire USB_PA7,
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[27] | 33 | inout wire [7:0] USB_PB,
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| 34 |
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| 35 | output wire RAM_CLK,
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| 36 | output wire RAM_CE1,
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| 37 | output wire RAM_WE,
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| 38 | output wire [19:0] RAM_ADDR,
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| 39 | inout wire RAM_DQAP,
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| 40 | inout wire [7:0] RAM_DQA,
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| 41 | inout wire RAM_DQBP,
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| 42 | inout wire [7:0] RAM_DQB
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| 43 | );
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| 44 |
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| 45 | // Turn output ports off
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| 46 | assign RAM_CLK = 1'b0;
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| 47 | assign RAM_CE1 = 1'b0;
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| 48 | assign RAM_WE = 1'b0;
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| 49 | assign RAM_ADDR = 20'h00000;
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| 50 |
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| 51 | // Turn inout ports to tri-state
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| 52 | assign TRG = 4'bz;
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| 53 | assign CON_A = 7'bz;
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| 54 | assign CON_B = 16'bz;
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| 55 | assign CON_C = 13'bz;
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[30] | 56 | assign USB_PA0 = 1'bz;
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| 57 | assign USB_PA1 = 1'bz;
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| 58 | assign USB_PA3 = 1'bz;
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| 59 | assign USB_PA7 = 1'bz;
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[27] | 60 | assign RAM_DQAP = 1'bz;
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| 61 | assign RAM_DQA = 8'bz;
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| 62 | assign RAM_DQBP = 1'bz;
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| 63 | assign RAM_DQB = 8'bz;
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| 64 |
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[30] | 65 |
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| 66 | assign USB_PA2 = ~usb_rden;
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| 67 | assign USB_PA4 = usb_addr[0];
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| 68 | assign USB_PA5 = usb_addr[1];
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| 69 | assign USB_PA6 = ~usb_pktend;
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| 70 |
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[27] | 71 | reg [31:0] counter;
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[31] | 72 | reg led_reg;
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[30] | 73 | // assign LED = counter[24];
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[31] | 74 | assign LED = led_reg;
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[27] | 75 |
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| 76 | wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
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[35] | 77 | wire usb_fifo_aclr;
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[30] | 78 | reg usb_fifo_tx_wrreq;
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| 79 | reg usb_fifo_rx_rdreq;
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[27] | 80 | wire usb_fifo_tx_full, usb_fifo_rx_empty;
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[30] | 81 | reg [7:0] usb_fifo_tx_data;
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| 82 | wire [7:0] usb_fifo_rx_data;
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[27] | 83 | wire [1:0] usb_addr;
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| 84 |
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| 85 | assign USB_SLRD = ~usb_rdreq;
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| 86 | assign USB_SLWR = ~usb_wrreq;
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| 87 |
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| 88 | usb_fifo usb_fifo_unit
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| 89 | (
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| 90 | .usb_clk(USB_IFCLK),
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| 91 | .usb_data(USB_PB),
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| 92 | .usb_full(~USB_FLAGB),
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| 93 | .usb_empty(~USB_FLAGA),
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| 94 | .usb_wrreq(usb_wrreq),
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| 95 | .usb_rdreq(usb_rdreq),
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| 96 | .usb_rden(usb_rden),
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| 97 | .usb_pktend(usb_pktend),
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| 98 | .usb_addr(usb_addr),
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[34] | 99 |
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[27] | 100 | .clk(CLK_50MHz),
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| 101 | .aclr(usb_fifo_aclr),
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[34] | 102 |
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| 103 | .tx_full(usb_fifo_tx_full),
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| 104 | .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
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[27] | 105 | .tx_data(usb_fifo_tx_data),
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[34] | 106 |
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[27] | 107 | .rx_empty(usb_fifo_rx_empty),
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[34] | 108 | .rx_rdreq(usb_fifo_rx_rdreq),
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[35] | 109 | .rx_q(usb_fifo_rx_data)
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[27] | 110 | );
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| 111 |
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[35] | 112 | reg [10:0] tst_counter;
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| 113 |
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| 114 | reg [9:0] osc_counter;
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[27] | 115 | reg osc_reset;
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[30] | 116 | reg osc_byte_num;
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[27] | 117 | wire [9:0] osc_start_addr;
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| 118 | reg [9:0] osc_addr;
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| 119 | wire [15:0] osc_q;
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| 120 |
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| 121 | reg hst_reset;
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[30] | 122 | reg [1:0] hst_byte_num;
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[27] | 123 | reg [11:0] hst_addr;
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| 124 | wire [31:0] hst_q;
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| 125 |
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[35] | 126 | reg [3:0] state0, state1, state2;
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[27] | 127 | reg adc_fifo_rdreq;
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| 128 | wire adc_fifo_rdempty;
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| 129 | reg adc_fifo_aclr;
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| 130 |
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| 131 | reg [31:0] adc_counter;
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| 132 | reg adc_data_ready;
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| 133 | wire adc_clk;
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| 134 | reg [11:0] adc_data;
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| 135 | wire [11:0] raw_data;
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| 136 | wire [11:0] uwt_data;
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| 137 | wire [1:0] uwt_flag;
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| 138 |
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| 139 | pll pll_unit(
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| 140 | .inclk0(CLK_50MHz),
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| 141 | .c0(adc_clk));
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| 142 |
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| 143 | adc_fifo adc_fifo_unit (
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| 144 | .adc_clk(adc_clk),
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| 145 | .adc_data(adc_data),
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| 146 | .aclr(adc_fifo_aclr),
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| 147 | .rdclk(CLK_50MHz),
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| 148 | .rdreq(adc_fifo_rdreq),
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| 149 | .rdempty(adc_fifo_rdempty),
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| 150 | .raw_data(raw_data),
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| 151 | .uwt_data({uwt_flag, uwt_data}));
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| 152 |
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| 153 | histogram histogram_unit (
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| 154 | .clk(CLK_50MHz),
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| 155 | .reset(hst_reset),
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| 156 | .data_ready(adc_data_ready),
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| 157 | .data(raw_data),
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| 158 | .address(hst_addr),
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| 159 | .q(hst_q)
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| 160 | );
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| 161 |
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| 162 | oscilloscope oscilloscope_unit (
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| 163 | .clk(CLK_50MHz),
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| 164 | .reset(osc_reset),
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| 165 | .data_ready(adc_data_ready),
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| 166 | .raw_data(raw_data),
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| 167 | .uwt_data(uwt_data),
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| 168 | .threshold(16'd100),
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| 169 | .address(osc_addr),
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| 170 | .start_address(osc_start_addr),
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| 171 | .q(osc_q)
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| 172 | );
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| 173 |
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[30] | 174 | /*
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[27] | 175 | always @ (posedge adc_clk)
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| 176 | begin
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| 177 | counter <= counter + 32'd1;
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| 178 | end
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[30] | 179 | */
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[27] | 180 |
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| 181 | always @ (posedge CLK_50MHz)
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| 182 | begin
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| 183 | case (state0)
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| 184 | 1:
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| 185 | begin
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| 186 | if (~adc_fifo_rdempty)
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| 187 | begin
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[30] | 188 | // adc_counter <= adc_counter + 32'd1;
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[27] | 189 | adc_fifo_rdreq <= 1'b1;
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| 190 | adc_data_ready <= 1'b1;
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[35] | 191 | state0 <= 4'd2;
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[27] | 192 | end
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| 193 | end
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| 194 |
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| 195 | 2:
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| 196 | begin
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| 197 | adc_fifo_rdreq <= 1'b0;
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| 198 | adc_data_ready <= 1'b0;
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[35] | 199 | state0 <= 4'd1;
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[27] | 200 | end
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| 201 |
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| 202 | default:
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| 203 | begin
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[35] | 204 | state0 <= 4'd1;
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[27] | 205 | end
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| 206 | endcase
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| 207 | end
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[35] | 208 |
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[30] | 209 | always @(posedge CLK_50MHz)
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| 210 | begin
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[35] | 211 | case(state1)
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[30] | 212 | 1:
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| 213 | begin
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| 214 | usb_fifo_rx_rdreq <= 1'b0;
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| 215 | usb_fifo_tx_wrreq <= 1'b0;
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| 216 | hst_reset <= 1'b0;
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| 217 | osc_reset <= 1'b0;
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[35] | 218 | state1 <= 4'd2;
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[30] | 219 | end
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| 220 |
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| 221 | 2:
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| 222 | begin
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[31] | 223 | usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
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[30] | 224 | if (~usb_fifo_rx_empty)
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| 225 | begin
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| 226 | case (usb_fifo_rx_data)
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| 227 | 8'h30:
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| 228 | begin
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| 229 | hst_reset <= 1'b1;
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[35] | 230 | state1 <= 4'd1;
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[30] | 231 | end
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| 232 | 8'h31:
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| 233 | begin
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| 234 | hst_addr <= 12'd0;
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| 235 | hst_byte_num <= 2'd0;
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[35] | 236 | state1 <= 4'd3;
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[30] | 237 | end
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| 238 | 8'h32:
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| 239 | begin
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[35] | 240 | led_reg <= 1'b1;
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[30] | 241 | osc_reset <= 1'b1;
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[35] | 242 | state1 <= 4'd1;
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[30] | 243 | end
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| 244 | 8'h33:
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| 245 | begin
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[31] | 246 | led_reg <= 1'b0;
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[30] | 247 | osc_addr <= osc_start_addr;
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| 248 | osc_counter <= 10'd0;
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| 249 | osc_byte_num <= 1'd0;
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[35] | 250 | state1 <= 4'd6;
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[30] | 251 | end
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[35] | 252 | 8'h34:
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| 253 | begin
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| 254 | led_reg <= 1'b1;
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| 255 | state1 <= 4'd1;
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| 256 | end
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| 257 | 8'h35:
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| 258 | begin
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| 259 | led_reg <= 1'b0;
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| 260 | tst_counter <= 11'd0;
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| 261 | state1 <= 4'd9;
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| 262 | end
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[30] | 263 | endcase
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| 264 | end
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| 265 | end
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| 266 |
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[35] | 267 | // hst transfer
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[30] | 268 | 3:
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| 269 | begin
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[35] | 270 | usb_fifo_tx_data <= hst_q[7:0];
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| 271 | usb_fifo_tx_wrreq <= 1'b1;
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| 272 | hst_byte_num <= 2'd1;
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| 273 | state1 <= 4'd4;
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| 274 | end
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| 275 | 4:
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| 276 | begin
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[30] | 277 | if (~usb_fifo_tx_full)
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| 278 | begin
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| 279 | case (hst_byte_num)
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| 280 | 2'd0: usb_fifo_tx_data <= hst_q[7:0];
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| 281 | 2'd1: usb_fifo_tx_data <= hst_q[15:8];
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| 282 | 2'd2: usb_fifo_tx_data <= hst_q[23:16];
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| 283 | 2'd3: usb_fifo_tx_data <= hst_q[31:24];
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| 284 | endcase
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[34] | 285 | if ((&hst_byte_num) & (&hst_addr))
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[30] | 286 | begin
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[35] | 287 | state1 <= 4'd5;
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[30] | 288 | end
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[35] | 289 | else
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[34] | 290 | begin
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[35] | 291 | if (&hst_byte_num)
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| 292 | begin
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| 293 | hst_addr <= hst_addr + 12'd1;
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| 294 | end
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| 295 | hst_byte_num <= hst_byte_num + 2'd1;
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[34] | 296 | end
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[30] | 297 | end
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| 298 | end
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[34] | 299 | 5:
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| 300 | begin
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| 301 | if (~usb_fifo_tx_full)
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| 302 | begin
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[35] | 303 | usb_fifo_tx_wrreq <= 1'b0;
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| 304 | state1 <= 4'd1;
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[34] | 305 | end
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| 306 | end
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| 307 |
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[35] | 308 | // osc transfer
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[34] | 309 | 6:
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| 310 | begin
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[35] | 311 | usb_fifo_tx_data <= osc_q[7:0];
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| 312 | usb_fifo_tx_wrreq <= 1'b1;
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| 313 | osc_byte_num <= 1'd1;
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| 314 | state1 <= 4'd7;
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[34] | 315 | end
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[35] | 316 | 7:
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[34] | 317 | begin
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[35] | 318 | if (~usb_fifo_tx_full)
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[30] | 319 | begin
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| 320 | case (osc_byte_num)
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| 321 | 1'd0: usb_fifo_tx_data <= osc_q[7:0];
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| 322 | 1'd1: usb_fifo_tx_data <= osc_q[15:8];
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| 323 | endcase
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[35] | 324 | if ((&osc_byte_num) & (&osc_counter))
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[30] | 325 | begin
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[35] | 326 | state1 <= 4'd8;
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[30] | 327 | end
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[35] | 328 | else
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[34] | 329 | begin
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[35] | 330 | if (&osc_byte_num)
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| 331 | begin
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| 332 | osc_addr <= osc_addr + 10'd1;
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| 333 | osc_counter <= osc_counter + 10'd1;
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| 334 | end
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| 335 | osc_byte_num <= osc_byte_num + 1'd1;
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[34] | 336 | end
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[30] | 337 | end
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| 338 | end
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[35] | 339 | 8:
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[30] | 340 | begin
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[35] | 341 | if (~usb_fifo_tx_full)
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[30] | 342 | begin
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[35] | 343 | usb_fifo_tx_wrreq <= 1'b0;
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| 344 | state1 <= 4'd1;
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[30] | 345 | end
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[34] | 346 | end
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[35] | 347 | // tst transfer
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| 348 | 9:
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[34] | 349 | begin
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[35] | 350 | usb_fifo_tx_data <= tst_counter;
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[34] | 351 | usb_fifo_tx_wrreq <= 1'b1;
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[35] | 352 | tst_counter <= tst_counter + 11'd1;
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| 353 | state1 <= 4'd10;
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[34] | 354 | end
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[35] | 355 | 10:
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[34] | 356 | begin
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| 357 | if (~usb_fifo_tx_full)
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[30] | 358 | begin
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[35] | 359 | usb_fifo_tx_data <= tst_counter;
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| 360 | if (tst_counter == 11'd0) //(&osc_counter)
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[34] | 361 | begin
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[35] | 362 | state1 <= 4'd11;
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[34] | 363 | end
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| 364 | else
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| 365 | begin
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[35] | 366 | tst_counter <= tst_counter + 11'd1;
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[34] | 367 | end
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[30] | 368 | end
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| 369 | end
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[35] | 370 | 11:
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[30] | 371 | begin
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[34] | 372 | if (~usb_fifo_tx_full)
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[30] | 373 | begin
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[34] | 374 | usb_fifo_tx_wrreq <= 1'b0;
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[35] | 375 | state1 <= 4'd1;
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[30] | 376 | end
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| 377 | end
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[35] | 378 |
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| 379 | default:
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| 380 | begin
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| 381 | state1 <= 4'd1;
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| 382 | end
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[30] | 383 | endcase
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| 384 | end
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[34] | 385 |
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[27] | 386 | always @ (posedge adc_clk)
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| 387 | begin
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| 388 | case (state2)
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| 389 | 1:
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| 390 | begin
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| 391 | adc_data <= 12'd0;
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[35] | 392 | state2 <= 4'd2;
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[27] | 393 | end
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| 394 |
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| 395 | 2:
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| 396 | begin
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| 397 | adc_data <= 12'd1024;
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[35] | 398 | state2 <= 4'd3;
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[27] | 399 | end
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| 400 |
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| 401 | 3:
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| 402 | begin
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| 403 | adc_data <= 12'd2048;
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[35] | 404 | state2 <= 4'd4;
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[27] | 405 | end
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| 406 |
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| 407 | 4:
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| 408 | begin
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| 409 | adc_data <= 12'd3072;
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[35] | 410 | state2 <= 4'd5;
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[27] | 411 | end
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| 412 |
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| 413 | 5:
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| 414 | begin
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| 415 | adc_data <= 12'd4095;
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[35] | 416 | state2 <= 4'd1;
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[27] | 417 | end
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| 418 |
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| 419 | default:
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| 420 | begin
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[35] | 421 | state2 <= 4'd1;
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[27] | 422 | end
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| 423 | endcase
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| 424 | end
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| 425 |
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| 426 | endmodule
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