source: trunk/MultiChannelUSB/Paella.v@ 37

Last change on this file since 37 was 37, checked in by demin, 15 years ago

fix communication with fifo_rx_unit
File size: 8.5 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46 assign RAM_CLK = 1'b0;
47 assign RAM_CE1 = 1'b0;
48 assign RAM_WE = 1'b0;
49 assign RAM_ADDR = 20'h00000;
50
51 // Turn inout ports to tri-state
52 assign TRG = 4'bz;
53 assign CON_A = 7'bz;
54 assign CON_B = 16'bz;
55 assign CON_C = 13'bz;
56 assign USB_PA0 = 1'bz;
57 assign USB_PA1 = 1'bz;
58 assign USB_PA3 = 1'bz;
59 assign USB_PA7 = 1'bz;
60 assign RAM_DQAP = 1'bz;
61 assign RAM_DQA = 8'bz;
62 assign RAM_DQBP = 1'bz;
63 assign RAM_DQB = 8'bz;
64
65
66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
71 reg [31:0] counter;
72 reg led_reg;
73// assign LED = counter[24];
74 assign LED = led_reg;
75
76 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
77 wire usb_fifo_aclr;
78 reg usb_fifo_tx_wrreq;
79 reg usb_fifo_rx_rdreq;
80 wire usb_fifo_tx_full, usb_fifo_rx_empty;
81 reg [7:0] usb_fifo_tx_data;
82 wire [7:0] usb_fifo_rx_data;
83 wire [1:0] usb_addr;
84
85 assign USB_SLRD = ~usb_rdreq;
86 assign USB_SLWR = ~usb_wrreq;
87
88 usb_fifo usb_fifo_unit
89 (
90 .usb_clk(USB_IFCLK),
91 .usb_data(USB_PB),
92 .usb_full(~USB_FLAGB),
93 .usb_empty(~USB_FLAGA),
94 .usb_wrreq(usb_wrreq),
95 .usb_rdreq(usb_rdreq),
96 .usb_rden(usb_rden),
97 .usb_pktend(usb_pktend),
98 .usb_addr(usb_addr),
99
100 .clk(CLK_50MHz),
101 .aclr(usb_fifo_aclr),
102
103 .tx_full(usb_fifo_tx_full),
104 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
105 .tx_data(usb_fifo_tx_data),
106
107 .rx_empty(usb_fifo_rx_empty),
108 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
109 .rx_q(usb_fifo_rx_data)
110 );
111
112 reg [23:0] rx_counter;
113 reg [10:0] tst_counter;
114
115 reg [9:0] osc_counter;
116 reg osc_reset;
117 reg osc_byte_num;
118 wire [9:0] osc_start_addr;
119 reg [9:0] osc_addr;
120 wire [15:0] osc_q;
121
122 reg hst_reset;
123 reg [1:0] hst_byte_num;
124 reg [11:0] hst_addr;
125 wire [31:0] hst_q;
126
127 reg [3:0] state0, state1, state2;
128 reg adc_fifo_rdreq;
129 wire adc_fifo_rdempty;
130 reg adc_fifo_aclr;
131
132 reg [31:0] adc_counter;
133 reg adc_data_ready;
134 wire adc_clk;
135 reg [11:0] adc_data;
136 wire [11:0] raw_data;
137 wire [11:0] uwt_data;
138 wire [1:0] uwt_flag;
139
140 pll pll_unit(
141 .inclk0(CLK_50MHz),
142 .c0(adc_clk));
143
144 adc_fifo adc_fifo_unit (
145 .adc_clk(adc_clk),
146 .adc_data(adc_data),
147 .aclr(adc_fifo_aclr),
148 .rdclk(CLK_50MHz),
149 .rdreq(adc_fifo_rdreq),
150 .rdempty(adc_fifo_rdempty),
151 .raw_data(raw_data),
152 .uwt_data({uwt_flag, uwt_data}));
153
154 histogram histogram_unit (
155 .clk(CLK_50MHz),
156 .reset(hst_reset),
157 .data_ready(adc_data_ready),
158 .data(raw_data),
159 .address(hst_addr),
160 .q(hst_q)
161 );
162
163 oscilloscope oscilloscope_unit (
164 .clk(CLK_50MHz),
165 .reset(osc_reset),
166 .data_ready(adc_data_ready),
167 .raw_data(raw_data),
168 .uwt_data(uwt_data),
169 .threshold(16'd100),
170 .address(osc_addr),
171 .start_address(osc_start_addr),
172 .q(osc_q)
173 );
174
175/*
176 always @ (posedge adc_clk)
177 begin
178 counter <= counter + 32'd1;
179 end
180*/
181
182 always @ (posedge CLK_50MHz)
183 begin
184 case (state0)
185 1:
186 begin
187 if (~adc_fifo_rdempty)
188 begin
189// adc_counter <= adc_counter + 32'd1;
190 adc_fifo_rdreq <= 1'b1;
191 adc_data_ready <= 1'b1;
192 state0 <= 4'd2;
193 end
194 end
195
196 2:
197 begin
198 adc_fifo_rdreq <= 1'b0;
199 adc_data_ready <= 1'b0;
200 state0 <= 4'd1;
201 end
202
203 default:
204 begin
205 state0 <= 4'd1;
206 end
207 endcase
208 end
209
210 always @(posedge CLK_50MHz)
211 begin
212 if (~usb_fifo_rx_empty)
213 begin
214 led_reg <= 1'b0;
215 rx_counter <= 24'd0;
216 end
217 else
218 begin
219 if (&rx_counter)
220 begin
221 led_reg <= 1'b1;
222 end
223 else
224 begin
225 rx_counter <= rx_counter + 24'd1;
226 end
227 end
228
229 case(state1)
230 1:
231 begin
232 usb_fifo_rx_rdreq <= 1'b1;
233 usb_fifo_tx_wrreq <= 1'b0;
234 hst_reset <= 1'b0;
235 osc_reset <= 1'b0;
236 state1 <= 4'd2;
237 end
238
239 2:
240 begin
241 if (~usb_fifo_rx_empty)
242 begin
243 case (usb_fifo_rx_data)
244 8'h30:
245 begin
246 usb_fifo_rx_rdreq <= 1'b0;
247 hst_reset <= 1'b1;
248 state1 <= 4'd1;
249 end
250 8'h31:
251 begin
252 usb_fifo_rx_rdreq <= 1'b0;
253 hst_addr <= 12'd0;
254 hst_byte_num <= 2'd0;
255 state1 <= 4'd3;
256 end
257 8'h32:
258 begin
259 usb_fifo_rx_rdreq <= 1'b0;
260 osc_reset <= 1'b1;
261 state1 <= 4'd1;
262 end
263 8'h33:
264 begin
265 usb_fifo_rx_rdreq <= 1'b0;
266 osc_addr <= osc_start_addr;
267 osc_counter <= 10'd0;
268 osc_byte_num <= 1'd0;
269 state1 <= 4'd6;
270 end
271 8'h34:
272 begin
273 usb_fifo_rx_rdreq <= 1'b0;
274 state1 <= 4'd1;
275 end
276 8'h35:
277 begin
278 usb_fifo_rx_rdreq <= 1'b0;
279 tst_counter <= 11'd0;
280 state1 <= 4'd9;
281 end
282 endcase
283 end
284 end
285
286 // hst transfer
287 3:
288 begin
289 usb_fifo_tx_data <= hst_q[7:0];
290 usb_fifo_tx_wrreq <= 1'b1;
291 hst_byte_num <= 2'd1;
292 state1 <= 4'd4;
293 end
294 4:
295 begin
296 if (~usb_fifo_tx_full)
297 begin
298 case (hst_byte_num)
299 2'd0: usb_fifo_tx_data <= hst_q[7:0];
300 2'd1: usb_fifo_tx_data <= hst_q[15:8];
301 2'd2: usb_fifo_tx_data <= hst_q[23:16];
302 2'd3: usb_fifo_tx_data <= hst_q[31:24];
303 endcase
304 if ((&hst_byte_num) & (&hst_addr))
305 begin
306 state1 <= 4'd5;
307 end
308 else
309 begin
310 if (&hst_byte_num)
311 begin
312 hst_addr <= hst_addr + 12'd1;
313 end
314 hst_byte_num <= hst_byte_num + 2'd1;
315 end
316 end
317 end
318 5:
319 begin
320 if (~usb_fifo_tx_full)
321 begin
322 usb_fifo_tx_wrreq <= 1'b0;
323 state1 <= 4'd1;
324 end
325 end
326
327 // osc transfer
328 6:
329 begin
330 usb_fifo_tx_data <= osc_q[7:0];
331 usb_fifo_tx_wrreq <= 1'b1;
332 osc_byte_num <= 1'd1;
333 state1 <= 4'd7;
334 end
335 7:
336 begin
337 if (~usb_fifo_tx_full)
338 begin
339 case (osc_byte_num)
340 1'd0: usb_fifo_tx_data <= osc_q[7:0];
341 1'd1: usb_fifo_tx_data <= osc_q[15:8];
342 endcase
343 if ((&osc_byte_num) & (&osc_counter))
344 begin
345 state1 <= 4'd8;
346 end
347 else
348 begin
349 if (&osc_byte_num)
350 begin
351 osc_addr <= osc_addr + 10'd1;
352 osc_counter <= osc_counter + 10'd1;
353 end
354 osc_byte_num <= osc_byte_num + 1'd1;
355 end
356 end
357 end
358 8:
359 begin
360 if (~usb_fifo_tx_full)
361 begin
362 usb_fifo_tx_wrreq <= 1'b0;
363 state1 <= 4'd1;
364 end
365 end
366 // tst transfer
367 9:
368 begin
369 usb_fifo_tx_data <= tst_counter;
370 usb_fifo_tx_wrreq <= 1'b1;
371 tst_counter <= tst_counter + 11'd1;
372 state1 <= 4'd10;
373 end
374 10:
375 begin
376 if (~usb_fifo_tx_full)
377 begin
378 usb_fifo_tx_data <= tst_counter;
379 if (tst_counter == 11'd0) //(&osc_counter)
380 begin
381 state1 <= 4'd11;
382 end
383 else
384 begin
385 tst_counter <= tst_counter + 11'd1;
386 end
387 end
388 end
389 11:
390 begin
391 if (~usb_fifo_tx_full)
392 begin
393 usb_fifo_tx_wrreq <= 1'b0;
394 state1 <= 4'd1;
395 end
396 end
397
398 default:
399 begin
400 state1 <= 4'd1;
401 end
402 endcase
403 end
404
405 always @ (posedge adc_clk)
406 begin
407 case (state2)
408 1:
409 begin
410 adc_data <= 12'd0;
411 state2 <= 4'd2;
412 end
413
414 2:
415 begin
416 adc_data <= 12'd1024;
417 state2 <= 4'd3;
418 end
419
420 3:
421 begin
422 adc_data <= 12'd2048;
423 state2 <= 4'd4;
424 end
425
426 4:
427 begin
428 adc_data <= 12'd3072;
429 state2 <= 4'd5;
430 end
431
432 5:
433 begin
434 adc_data <= 12'd4095;
435 state2 <= 4'd1;
436 end
437
438 default:
439 begin
440 state2 <= 4'd1;
441 end
442 endcase
443 end
444
445endmodule
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