source: trunk/MultiChannelUSB/Paella.v@ 32

Last change on this file since 32 was 31, checked in by demin, 15 years ago

attemp to improve USB interface
File size: 7.8 KB
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[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
[30]25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
[27]33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46 assign RAM_CLK = 1'b0;
47 assign RAM_CE1 = 1'b0;
48 assign RAM_WE = 1'b0;
49 assign RAM_ADDR = 20'h00000;
50
51 // Turn inout ports to tri-state
52 assign TRG = 4'bz;
53 assign CON_A = 7'bz;
54 assign CON_B = 16'bz;
55 assign CON_C = 13'bz;
[30]56 assign USB_PA0 = 1'bz;
57 assign USB_PA1 = 1'bz;
58 assign USB_PA3 = 1'bz;
59 assign USB_PA7 = 1'bz;
[27]60 assign RAM_DQAP = 1'bz;
61 assign RAM_DQA = 8'bz;
62 assign RAM_DQBP = 1'bz;
63 assign RAM_DQB = 8'bz;
64
[30]65
66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
[27]71 reg [31:0] counter;
[31]72 reg led_reg;
[30]73// assign LED = counter[24];
[31]74// assign LED = ~usb_fifo_rx_empty;
75 assign LED = led_reg;
76// assign LED = usb_fifo_led;
[27]77
78 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
79 wire usb_fifo_aclr, usb_fifo_led;
[30]80 reg usb_fifo_tx_wrreq;
81 reg usb_fifo_rx_rdreq;
[27]82 wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]83 reg [7:0] usb_fifo_tx_data;
84 wire [7:0] usb_fifo_rx_data;
[27]85 wire [1:0] usb_addr;
86
87 assign USB_SLRD = ~usb_rdreq;
88 assign USB_SLWR = ~usb_wrreq;
89
90 usb_fifo usb_fifo_unit
91 (
92 .usb_clk(USB_IFCLK),
93 .usb_data(USB_PB),
94 .usb_full(~USB_FLAGB),
95 .usb_empty(~USB_FLAGA),
96 .usb_wrreq(usb_wrreq),
97 .usb_rdreq(usb_rdreq),
98 .usb_rden(usb_rden),
99 .usb_pktend(usb_pktend),
100 .usb_addr(usb_addr),
101 .clk(CLK_50MHz),
102 .aclr(usb_fifo_aclr),
103 .tx_wrreq(usb_fifo_tx_wrreq),
104 .rx_rdreq(usb_fifo_rx_rdreq),
105 .tx_data(usb_fifo_tx_data),
106 .tx_full(usb_fifo_tx_full),
107 .rx_empty(usb_fifo_rx_empty),
[31]108 .rx_data(usb_fifo_rx_data),
109 .led(usb_fifo_led)
[27]110 );
111
112 reg [9:0] osc_counter;
113 reg osc_reset;
[30]114 reg osc_byte_num;
[27]115 wire [9:0] osc_start_addr;
116 reg [9:0] osc_addr;
117 wire [15:0] osc_q;
118
119 reg hst_reset;
[30]120 reg [1:0] hst_byte_num;
[27]121 reg [11:0] hst_addr;
122 wire [31:0] hst_q;
123
[30]124 reg [2:0] state0, state1, state2;
[27]125 reg adc_fifo_rdreq;
126 wire adc_fifo_rdempty;
127 reg adc_fifo_aclr;
128
129 reg [31:0] adc_counter;
130 reg adc_data_ready;
131 wire adc_clk;
132 reg [11:0] adc_data;
133 wire [11:0] raw_data;
134 wire [11:0] uwt_data;
135 wire [1:0] uwt_flag;
136
137 pll pll_unit(
138 .inclk0(CLK_50MHz),
139 .c0(adc_clk));
140
141 adc_fifo adc_fifo_unit (
142 .adc_clk(adc_clk),
143 .adc_data(adc_data),
144 .aclr(adc_fifo_aclr),
145 .rdclk(CLK_50MHz),
146 .rdreq(adc_fifo_rdreq),
147 .rdempty(adc_fifo_rdempty),
148 .raw_data(raw_data),
149 .uwt_data({uwt_flag, uwt_data}));
150
151 histogram histogram_unit (
152 .clk(CLK_50MHz),
153 .reset(hst_reset),
154 .data_ready(adc_data_ready),
155 .data(raw_data),
156 .address(hst_addr),
157 .q(hst_q)
158 );
159
160 oscilloscope oscilloscope_unit (
161 .clk(CLK_50MHz),
162 .reset(osc_reset),
163 .data_ready(adc_data_ready),
164 .raw_data(raw_data),
165 .uwt_data(uwt_data),
166 .threshold(16'd100),
167 .address(osc_addr),
168 .start_address(osc_start_addr),
169 .q(osc_q)
170 );
171
[30]172/*
[27]173 always @ (posedge adc_clk)
174 begin
175 counter <= counter + 32'd1;
176 end
[30]177*/
[27]178
179 always @ (posedge CLK_50MHz)
180 begin
181 case (state0)
182 1:
183 begin
184 if (~adc_fifo_rdempty)
185 begin
[30]186// adc_counter <= adc_counter + 32'd1;
[27]187 adc_fifo_rdreq <= 1'b1;
188 adc_data_ready <= 1'b1;
[30]189 state0 <= 3'd2;
[27]190 end
191 end
192
193 2:
194 begin
195 adc_fifo_rdreq <= 1'b0;
196 adc_data_ready <= 1'b0;
[30]197 state0 <= 3'd1;
[27]198 end
199
200 default:
201 begin
[30]202 state0 <= 3'd1;
[27]203 end
204 endcase
205 end
206
[30]207 always @(posedge CLK_50MHz)
208 begin
209 case (state1)
210 1:
211 begin
212 usb_fifo_rx_rdreq <= 1'b0;
213 usb_fifo_tx_wrreq <= 1'b0;
214 hst_reset <= 1'b0;
215 osc_reset <= 1'b0;
216 state1 <= 3'd2;
217 end
218
219 2:
220 begin
[31]221 usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
[30]222 if (~usb_fifo_rx_empty)
223 begin
224 case (usb_fifo_rx_data)
225 8'h30:
226 begin
227 hst_reset <= 1'b1;
228 state1 <= 3'd1;
229 end
230 8'h31:
231 begin
[31]232 led_reg <= 1'b1;
[30]233 hst_addr <= 12'd0;
234 hst_byte_num <= 2'd0;
235 state1 <= 3'd3;
236 end
237 8'h32:
238 begin
239 osc_reset <= 1'b1;
240 state1 <= 3'd1;
241 end
242 8'h33:
243 begin
[31]244 led_reg <= 1'b0;
[30]245 osc_addr <= osc_start_addr;
246 osc_counter <= 10'd0;
247 osc_byte_num <= 1'd0;
248 state1 <= 3'd4;
249 end
[31]250
[30]251 endcase
252 end
253 end
254
255 3:
256 begin
257 // hst transfer
[31]258 usb_fifo_rx_rdreq <= 1'b0;
259 usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
[30]260 if (~usb_fifo_tx_full)
261 begin
262 case (hst_byte_num)
263 2'd0: usb_fifo_tx_data <= hst_q[7:0];
264 2'd1: usb_fifo_tx_data <= hst_q[15:8];
265 2'd2: usb_fifo_tx_data <= hst_q[23:16];
266 2'd3: usb_fifo_tx_data <= hst_q[31:24];
267 endcase
268
269 if (&hst_byte_num)
270 begin
271 if (&hst_addr)
272 begin
273 state1 <= 3'd1;
274 end
275 else
276 begin
277 hst_addr <= hst_addr + 12'd1;
278 end
279 end
[31]280
281 hst_byte_num <= hst_byte_num + 2'd1;
[30]282 end
283 end
284
285 4:
286 begin
287 // osc transfer
[31]288 usb_fifo_rx_rdreq <= 1'b0;
289 usb_fifo_tx_wrreq <= ~usb_fifo_tx_full;
[30]290 if(~usb_fifo_tx_full)
291 begin
292 case (osc_byte_num)
293 1'd0: usb_fifo_tx_data <= osc_q[7:0];
294 1'd1: usb_fifo_tx_data <= osc_q[15:8];
295 endcase
296
297 if (osc_byte_num)
298 begin
299 if (&osc_counter)
300 begin
301 state1 <= 3'd1;
302 end
303 else
304 begin
305 osc_addr <= osc_addr + 10'd1;
306 osc_counter <= osc_counter + 10'd1;
307 end
308 end
[31]309
310 osc_byte_num <= ~osc_byte_num;
[30]311 end
312 end
313
314 default:
315 begin
316 // default state is the first one
317 state1 <= 3'd1;
318 end
319 endcase
320 end
[31]321
[30]322/*
323 always @(posedge CLK_50MHz)
324 begin
325 case(state1)
326 0:
327 begin
328 usb_fifo_tx_wrreq <= 1'b0;
329 counter <= 32'd0;
330 state1 <= 3'd1;
331 end
332 1:
333 begin
334 if((~usb_fifo_tx_full) & (counter < 32'd512))
335 begin
336 counter <= counter + 32'd1;
337 state1 <= 3'd2;
338 usb_fifo_tx_data <= 1;
339 usb_fifo_tx_wrreq <= 1'b1;
340 end
341 else
342 begin
343 usb_fifo_tx_wrreq <= 1'b0;
344 end
345 end
346
347 2:
348 begin
349 if((~usb_fifo_tx_full) & (counter < 32'd512))
350 begin
351 counter <= counter + 32'd1;
352 state1 <= 3'd1;
353 usb_fifo_tx_data <= 0;
354 usb_fifo_tx_wrreq <= 1'b1;
355 end
356 else
357 begin
358 usb_fifo_tx_wrreq <= 1'b0;
359 end
360 end
361
362 default: state1 <= 3'd0;
363 endcase
364 end
365*/
[27]366 always @ (posedge adc_clk)
367 begin
368 case (state2)
369 1:
370 begin
371 adc_data <= 12'd0;
[30]372 state2 <= 3'd2;
[27]373 end
374
375 2:
376 begin
377 adc_data <= 12'd1024;
[30]378 state2 <= 3'd3;
[27]379 end
380
381 3:
382 begin
383 adc_data <= 12'd2048;
[30]384 state2 <= 3'd4;
[27]385 end
386
387 4:
388 begin
389 adc_data <= 12'd3072;
[30]390 state2 <= 3'd5;
[27]391 end
392
393 5:
394 begin
395 adc_data <= 12'd4095;
[30]396 state2 <= 3'd1;
[27]397 end
398
399 default:
400 begin
[30]401 state2 <= 3'd1;
[27]402 end
403 endcase
404 end
405
406endmodule
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