Changeset 91 for trunk

Timestamp:

Feb 28, 2010, 11:35:16 PM (15 years ago)

Author:

demin

Message:

fix communication with external SRAM

Location:

trunk/MultiChannelUSB

Files:

• configuration.v (modified) (2 diffs)
• control.v (modified) (5 diffs)
• oscilloscope.v (modified) (10 diffs)

trunk/MultiChannelUSB/configuration.v

@@ -15 +15 @@
         wire    [15:0]  int_ssel_wire;
         wire    [15:0]  int_miso_wire;
-        reg             [15:0]  int_miso_reg [3:0];
+        reg             [15:0]  int_miso_reg;
 
         wire    [15:0]  int_q_wire [15:0];
@@ -69 +69 @@
                 if (reset)
                 begin
-                        for(i = 0; i <= 3; i = i + 1)
-                        begin
-                                int_miso_reg[i] <= 16'd0;
-                        end
+                        int_miso_reg <= 16'd0;
                 end
                 else
                 begin
-                        for(i = 0; i < 3; i = i + 1)
-                        begin
-                                int_miso_reg[i+1] <= int_miso_reg[i];
-                        end
-                        int_miso_reg[0] <= int_miso_wire;
+                        int_miso_reg <= int_miso_wire;
                 end
         end
 
         // output logic
-        assign  bus_miso = int_miso_reg[3];
+        assign  bus_miso = int_miso_reg;
         assign  bus_busy = 1'b0;
         assign  cfg_bits = int_bits_wire;

trunk/MultiChannelUSB/control.v

@@ -183 +183 @@
                                         buffer[1] <= 8'd0;
                                         int_bus_cntr <= 32'd0;
-                                        state <= 5'd7;
                                 end
                                 else
                                 begin
-                                        buffer[0] <= 8'd2;
+                                        buffer[0] <= 8'd0;
                                         buffer[1] <= 8'd0;
-                                        state <= 5'd6;
-                                end
+                                end
+                                state <= 5'd7;
                         end
 
@@ -197 +196 @@
                                 buffer[0] <= bus_miso[7:0];
                                 buffer[1] <= bus_miso[15:8];
+                                int_bus_addr <= int_bus_addr + 32'd1;
+                                int_bus_cntr <= int_bus_cntr - 32'd1;
                                 state <= 5'd6;
                         end
@@ -202 +203 @@
                         6:
                         begin
-                                int_bus_addr <= int_bus_addr + 32'd1;
                                 state <= 5'd7;
                         end
@@ -208 +208 @@
                         7:
                         begin
+                                int_data <= buffer[0];
+                                int_wrreq <= 1'b1;
+                                state <= 5'd8;
+                        end
+
+                        8:
+                        begin
                                 if (~tx_full)
                                 begin
-                                        int_data <= buffer[0];
-                                        int_wrreq <= 1'b1;
-                                        state <= 5'd8;
-                                end
-                        end
-
-                        8:
-                        begin
-                                int_data <= buffer[1];
-                                state <= 5'd9;
+                                        int_data <= buffer[1];
+                                        state <= 5'd9;
+                                end
                         end
 
@@ -227 +227 @@
                                 begin
                                         int_wrreq <= 1'b0;
-                                        if (|int_bus_cntr)
-                                        begin
-                                                state <= 5'd5;
-                                                int_bus_cntr <= int_bus_cntr - 32'd1;
-                                        end
-                                        else
-                                        begin
-                                                state <= 5'd0;
-                                        end
+                                        state <= 5'd10;
+                                end
+                        end
+
+                        10:
+                        begin
+                                if (|int_bus_cntr)
+                                begin
+                                        state <= 5'd5;
+                                end
+                                else
+                                begin
+                                        state <= 5'd0;
                                 end
                         end

trunk/MultiChannelUSB/oscilloscope.v

@@ -24 +24 @@
         reg             [47:0]  osc_data_reg, osc_data_next;
 
-        reg             [19:0]  cfg_cntr_max_reg, cfg_cntr_max_next;
-        reg             [19:0]  cfg_cntr_mid_reg, cfg_cntr_mid_next;
-
         reg             [2:0]   int_case_reg, int_case_next;
 
         reg                             int_trig_reg, int_trig_next;
         reg             [19:0]  int_trig_addr_reg, int_trig_addr_next;
-        reg             [19:0]  int_cntr_reg, int_cntr_next;
+
+        reg             [19:0]  int_cntr_reg [1:0];
+        reg             [19:0]  int_cntr_next [1:0];
 
         reg             [15:0]  bus_mosi_reg [2:0];
@@ -71 +70 @@
                         bus_busy_reg <= 1'b0;
                         int_case_reg <= 5'd0;
-                        int_cntr_reg <= 20'd0;
+                        int_cntr_reg[0] <= 20'd0;
+                        int_cntr_reg[1] <= 20'd0;
                         int_trig_reg <= 1'b0;
                         int_trig_addr_reg <= 20'd0;
-                        cfg_cntr_max_reg <= 20'd0;
-                        cfg_cntr_mid_reg <= 20'd0;
                         
                         for(i = 0; i <= 2; i = i + 1)
@@ -91 +89 @@
                         bus_busy_reg <= bus_busy_next;
                         int_case_reg <= int_case_next;
-                        int_cntr_reg <= int_cntr_next;
+                        int_cntr_reg[0] <= int_cntr_next[0];
+                        int_cntr_reg[1] <= int_cntr_next[1];
                         int_trig_reg <= int_trig_next;
                         int_trig_addr_reg <= int_trig_addr_next;
-                        cfg_cntr_max_reg <= cfg_cntr_max_next;
-                        cfg_cntr_mid_reg <= cfg_cntr_mid_next;
 
                         for(i = 0; i <= 2; i = i + 1)
@@ -104 +101 @@
                 end
         end
-                
 
         always @*
@@ -115 +111 @@
                 bus_busy_next = bus_busy_reg;
                 int_case_next = int_case_reg;
-                int_cntr_next = int_cntr_reg;
+                int_cntr_next[0] = int_cntr_reg[0];
+                int_cntr_next[1] = int_cntr_reg[1];
                 int_trig_next = int_trig_reg;
                 int_trig_addr_next = int_trig_addr_reg;
-                cfg_cntr_max_next = cfg_cntr_max_reg;
-                cfg_cntr_mid_next = cfg_cntr_mid_reg;
 
                 for(i = 0; i < 2; i = i + 1)
@@ -135 +130 @@
                                 ram_addr_next = 20'd0;
                                 bus_busy_next = 1'b0;
-                                int_cntr_next = 20'd0;
+                                int_cntr_next[0] = 20'd0;
+                                int_cntr_next[1] = 20'd0;
                                 int_trig_next = 1'b0;
 
@@ -162 +158 @@
                                         int_case_next = 3'd1;
                                         int_trig_addr_next = 20'd0;
-                                        cfg_cntr_max_next = {cfg_data[7:0], 10'd0};
-                                        cfg_cntr_mid_next = {cfg_data[15:8], 10'd0};
+                                        int_cntr_next[0] = {cfg_data[7:0], 10'd0};
+                                        int_cntr_next[1] = {cfg_data[15:8], 10'd0};
                                 end
 
@@ -178 +174 @@
                                         int_case_next = 3'd2;
 
-                                        if ((~int_trig_reg) & (trg_flag) &
-                                                (int_cntr_reg == cfg_cntr_mid_reg))
+                                        if ((~int_trig_reg) & (trg_flag) & (int_cntr_reg[1] == 0))
                                         begin
                                                 int_trig_next = 1'b1;
@@ -185 +180 @@
                                         end
                                         
-                                        if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg))
-                                        begin
-                                                int_cntr_next = int_cntr_reg + 20'd1;
+                                        if ((int_trig_reg) & (|int_cntr_reg[0]))
+                                        begin
+                                                int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
+                                        end
+
+                                        if ((|int_cntr_reg[1]))
+                                        begin
+                                                int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
                                         end
                                 end
@@ -213 +213 @@
                                 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
                                 int_case_next = 3'd1;
-                                if (int_cntr_reg >= cfg_cntr_max_reg)
+                                if (int_cntr_reg[0] == 0)
                                 begin
                                         ram_wren_next[0] = 1'b0;