Changeset 91 for trunk/MultiChannelUSB/oscilloscope.v
- Timestamp:
- Feb 28, 2010, 11:35:16 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/oscilloscope.v
r90 r91 24 24 reg [47:0] osc_data_reg, osc_data_next; 25 25 26 reg [19:0] cfg_cntr_max_reg, cfg_cntr_max_next;27 reg [19:0] cfg_cntr_mid_reg, cfg_cntr_mid_next;28 29 26 reg [2:0] int_case_reg, int_case_next; 30 27 31 28 reg int_trig_reg, int_trig_next; 32 29 reg [19:0] int_trig_addr_reg, int_trig_addr_next; 33 reg [19:0] int_cntr_reg, int_cntr_next; 30 31 reg [19:0] int_cntr_reg [1:0]; 32 reg [19:0] int_cntr_next [1:0]; 34 33 35 34 reg [15:0] bus_mosi_reg [2:0]; … … 71 70 bus_busy_reg <= 1'b0; 72 71 int_case_reg <= 5'd0; 73 int_cntr_reg <= 20'd0; 72 int_cntr_reg[0] <= 20'd0; 73 int_cntr_reg[1] <= 20'd0; 74 74 int_trig_reg <= 1'b0; 75 75 int_trig_addr_reg <= 20'd0; 76 cfg_cntr_max_reg <= 20'd0;77 cfg_cntr_mid_reg <= 20'd0;78 76 79 77 for(i = 0; i <= 2; i = i + 1) … … 91 89 bus_busy_reg <= bus_busy_next; 92 90 int_case_reg <= int_case_next; 93 int_cntr_reg <= int_cntr_next; 91 int_cntr_reg[0] <= int_cntr_next[0]; 92 int_cntr_reg[1] <= int_cntr_next[1]; 94 93 int_trig_reg <= int_trig_next; 95 94 int_trig_addr_reg <= int_trig_addr_next; 96 cfg_cntr_max_reg <= cfg_cntr_max_next;97 cfg_cntr_mid_reg <= cfg_cntr_mid_next;98 95 99 96 for(i = 0; i <= 2; i = i + 1) … … 104 101 end 105 102 end 106 107 103 108 104 always @* … … 115 111 bus_busy_next = bus_busy_reg; 116 112 int_case_next = int_case_reg; 117 int_cntr_next = int_cntr_reg; 113 int_cntr_next[0] = int_cntr_reg[0]; 114 int_cntr_next[1] = int_cntr_reg[1]; 118 115 int_trig_next = int_trig_reg; 119 116 int_trig_addr_next = int_trig_addr_reg; 120 cfg_cntr_max_next = cfg_cntr_max_reg;121 cfg_cntr_mid_next = cfg_cntr_mid_reg;122 117 123 118 for(i = 0; i < 2; i = i + 1) … … 135 130 ram_addr_next = 20'd0; 136 131 bus_busy_next = 1'b0; 137 int_cntr_next = 20'd0; 132 int_cntr_next[0] = 20'd0; 133 int_cntr_next[1] = 20'd0; 138 134 int_trig_next = 1'b0; 139 135 … … 162 158 int_case_next = 3'd1; 163 159 int_trig_addr_next = 20'd0; 164 cfg_cntr_max_next= {cfg_data[7:0], 10'd0};165 cfg_cntr_mid_next= {cfg_data[15:8], 10'd0};160 int_cntr_next[0] = {cfg_data[7:0], 10'd0}; 161 int_cntr_next[1] = {cfg_data[15:8], 10'd0}; 166 162 end 167 163 … … 178 174 int_case_next = 3'd2; 179 175 180 if ((~int_trig_reg) & (trg_flag) & 181 (int_cntr_reg == cfg_cntr_mid_reg)) 176 if ((~int_trig_reg) & (trg_flag) & (int_cntr_reg[1] == 0)) 182 177 begin 183 178 int_trig_next = 1'b1; … … 185 180 end 186 181 187 if (int_trig_reg | (int_cntr_reg < cfg_cntr_mid_reg)) 188 begin 189 int_cntr_next = int_cntr_reg + 20'd1; 182 if ((int_trig_reg) & (|int_cntr_reg[0])) 183 begin 184 int_cntr_next[0] = int_cntr_reg[0] - 20'd1; 185 end 186 187 if ((|int_cntr_reg[1])) 188 begin 189 int_cntr_next[1] = int_cntr_reg[1] - 20'd1; 190 190 end 191 191 end … … 213 213 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0}; 214 214 int_case_next = 3'd1; 215 if (int_cntr_reg >= cfg_cntr_max_reg)215 if (int_cntr_reg[0] == 0) 216 216 begin 217 217 ram_wren_next[0] = 1'b0;
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