source: trunk/MultiChannelUSB/Paella.v@ 41

Last change on this file since 41 was 41, checked in by demin, 15 years ago

add one real ADC channel
File size: 9.0 KB
RevLine 
[27]1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
[41]15 input wire [2:0] ADC_D,
[27]16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
[30]23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
[27]31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
[30]54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
[27]58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
[30]63
64 assign USB_PA2 = ~usb_rden;
65 assign USB_PA4 = usb_addr[0];
66 assign USB_PA5 = usb_addr[1];
67 assign USB_PA6 = ~usb_pktend;
68
[27]69 reg [31:0] counter;
[31]70 reg led_reg;
[30]71// assign LED = counter[24];
[31]72 assign LED = led_reg;
[27]73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]75 wire usb_fifo_aclr;
[30]76 reg usb_fifo_tx_wrreq;
77 reg usb_fifo_rx_rdreq;
[27]78 wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]79 reg [7:0] usb_fifo_tx_data;
80 wire [7:0] usb_fifo_rx_data;
[27]81 wire [1:0] usb_addr;
82
83 assign USB_SLRD = ~usb_rdreq;
84 assign USB_SLWR = ~usb_wrreq;
85
86 usb_fifo usb_fifo_unit
87 (
88 .usb_clk(USB_IFCLK),
89 .usb_data(USB_PB),
90 .usb_full(~USB_FLAGB),
91 .usb_empty(~USB_FLAGA),
92 .usb_wrreq(usb_wrreq),
93 .usb_rdreq(usb_rdreq),
94 .usb_rden(usb_rden),
95 .usb_pktend(usb_pktend),
96 .usb_addr(usb_addr),
[34]97
[27]98 .clk(CLK_50MHz),
99 .aclr(usb_fifo_aclr),
[34]100
101 .tx_full(usb_fifo_tx_full),
102 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]103 .tx_data(usb_fifo_tx_data),
[34]104
[27]105 .rx_empty(usb_fifo_rx_empty),
[37]106 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]107 .rx_q(usb_fifo_rx_data)
[27]108 );
109
[37]110 reg [23:0] rx_counter;
[35]111 reg [10:0] tst_counter;
112
113 reg [9:0] osc_counter;
[27]114 reg osc_reset;
[30]115 reg osc_byte_num;
[27]116 wire [9:0] osc_start_addr;
117 reg [9:0] osc_addr;
118 wire [15:0] osc_q;
119
120 reg hst_reset;
[30]121 reg [1:0] hst_byte_num;
[27]122 reg [11:0] hst_addr;
123 wire [31:0] hst_q;
124
[35]125 reg [3:0] state0, state1, state2;
[27]126 reg adc_fifo_rdreq;
127 wire adc_fifo_rdempty;
128 reg adc_fifo_aclr;
129
130 reg [31:0] adc_counter;
131 reg adc_data_ready;
132 wire adc_clk;
[41]133
[27]134 reg [11:0] adc_data;
[41]135
136 wire adc_lvds_clk;
137 wire [11:0] adc_lvds_data [2:0];
138
[27]139 wire [11:0] raw_data;
140 wire [11:0] uwt_data;
141 wire [1:0] uwt_flag;
142
143 pll pll_unit(
144 .inclk0(CLK_50MHz),
145 .c0(adc_clk));
[41]146/*
[38]147 altserial_flash_loader #(
148 .enable_shared_access("OFF"),
149 .enhanced_mode(1),
150 .intended_device_family("Cyclone III")) sfl_unit (
151 .noe(1'b0),
152 .asmi_access_granted(),
153 .asmi_access_request(),
154 .data0out(),
155 .dclkin(),
156 .scein(),
157 .sdoin());
[41]158*/
159 adc_lvds adc_lvds_unit (
160 .lvds_dco(ADC_DCO),
161 .lvds_fco(ADC_FCO),
162 .lvds_d(ADC_D),
163 .adc_clk(adc_lvds_clk),
164 .adc_db(adc_lvds_data[0]),
165 .adc_dc(adc_lvds_data[1]),
166 .adc_dd(adc_lvds_data[2]));
[38]167
[27]168 adc_fifo adc_fifo_unit (
[41]169 .adc_clk(adc_lvds_clk),
170 .adc_data(adc_lvds_data[1]),
[27]171 .aclr(adc_fifo_aclr),
172 .rdclk(CLK_50MHz),
173 .rdreq(adc_fifo_rdreq),
174 .rdempty(adc_fifo_rdempty),
175 .raw_data(raw_data),
176 .uwt_data({uwt_flag, uwt_data}));
177
178 histogram histogram_unit (
179 .clk(CLK_50MHz),
180 .reset(hst_reset),
181 .data_ready(adc_data_ready),
182 .data(raw_data),
183 .address(hst_addr),
[41]184 .q(hst_q));
[27]185
186 oscilloscope oscilloscope_unit (
187 .clk(CLK_50MHz),
188 .reset(osc_reset),
189 .data_ready(adc_data_ready),
190 .raw_data(raw_data),
191 .uwt_data(uwt_data),
192 .threshold(16'd100),
193 .address(osc_addr),
194 .start_address(osc_start_addr),
[41]195 .q(osc_q));
[27]196
[30]197/*
[27]198 always @ (posedge adc_clk)
199 begin
200 counter <= counter + 32'd1;
201 end
[30]202*/
[27]203
204 always @ (posedge CLK_50MHz)
205 begin
206 case (state0)
207 1:
208 begin
209 if (~adc_fifo_rdempty)
210 begin
[30]211// adc_counter <= adc_counter + 32'd1;
[27]212 adc_fifo_rdreq <= 1'b1;
213 adc_data_ready <= 1'b1;
[35]214 state0 <= 4'd2;
[27]215 end
216 end
217
218 2:
219 begin
220 adc_fifo_rdreq <= 1'b0;
221 adc_data_ready <= 1'b0;
[35]222 state0 <= 4'd1;
[27]223 end
224
225 default:
226 begin
[35]227 state0 <= 4'd1;
[27]228 end
229 endcase
230 end
[35]231
[30]232 always @(posedge CLK_50MHz)
233 begin
[37]234 if (~usb_fifo_rx_empty)
235 begin
236 led_reg <= 1'b0;
237 rx_counter <= 24'd0;
238 end
239 else
240 begin
241 if (&rx_counter)
242 begin
243 led_reg <= 1'b1;
244 end
245 else
246 begin
247 rx_counter <= rx_counter + 24'd1;
248 end
249 end
250
[35]251 case(state1)
[30]252 1:
253 begin
[37]254 usb_fifo_rx_rdreq <= 1'b1;
[30]255 usb_fifo_tx_wrreq <= 1'b0;
256 hst_reset <= 1'b0;
257 osc_reset <= 1'b0;
[35]258 state1 <= 4'd2;
[30]259 end
260
261 2:
262 begin
263 if (~usb_fifo_rx_empty)
264 begin
265 case (usb_fifo_rx_data)
266 8'h30:
267 begin
[37]268 usb_fifo_rx_rdreq <= 1'b0;
[30]269 hst_reset <= 1'b1;
[35]270 state1 <= 4'd1;
[30]271 end
272 8'h31:
273 begin
[37]274 usb_fifo_rx_rdreq <= 1'b0;
[30]275 hst_addr <= 12'd0;
276 hst_byte_num <= 2'd0;
[35]277 state1 <= 4'd3;
[30]278 end
279 8'h32:
280 begin
[37]281 usb_fifo_rx_rdreq <= 1'b0;
[30]282 osc_reset <= 1'b1;
[35]283 state1 <= 4'd1;
[30]284 end
285 8'h33:
286 begin
[37]287 usb_fifo_rx_rdreq <= 1'b0;
[30]288 osc_addr <= osc_start_addr;
289 osc_counter <= 10'd0;
290 osc_byte_num <= 1'd0;
[35]291 state1 <= 4'd6;
[30]292 end
[35]293 8'h34:
294 begin
[37]295 usb_fifo_rx_rdreq <= 1'b0;
[35]296 state1 <= 4'd1;
297 end
298 8'h35:
299 begin
[37]300 usb_fifo_rx_rdreq <= 1'b0;
[35]301 tst_counter <= 11'd0;
302 state1 <= 4'd9;
303 end
[30]304 endcase
305 end
306 end
307
[35]308 // hst transfer
[30]309 3:
310 begin
[35]311 usb_fifo_tx_data <= hst_q[7:0];
312 usb_fifo_tx_wrreq <= 1'b1;
313 hst_byte_num <= 2'd1;
314 state1 <= 4'd4;
315 end
316 4:
317 begin
[30]318 if (~usb_fifo_tx_full)
319 begin
320 case (hst_byte_num)
321 2'd0: usb_fifo_tx_data <= hst_q[7:0];
322 2'd1: usb_fifo_tx_data <= hst_q[15:8];
323 2'd2: usb_fifo_tx_data <= hst_q[23:16];
324 2'd3: usb_fifo_tx_data <= hst_q[31:24];
325 endcase
[34]326 if ((&hst_byte_num) & (&hst_addr))
[30]327 begin
[35]328 state1 <= 4'd5;
[30]329 end
[35]330 else
[34]331 begin
[35]332 if (&hst_byte_num)
333 begin
334 hst_addr <= hst_addr + 12'd1;
335 end
336 hst_byte_num <= hst_byte_num + 2'd1;
[34]337 end
[30]338 end
339 end
[34]340 5:
341 begin
342 if (~usb_fifo_tx_full)
343 begin
[35]344 usb_fifo_tx_wrreq <= 1'b0;
345 state1 <= 4'd1;
[34]346 end
347 end
348
[35]349 // osc transfer
[34]350 6:
351 begin
[35]352 usb_fifo_tx_data <= osc_q[7:0];
353 usb_fifo_tx_wrreq <= 1'b1;
354 osc_byte_num <= 1'd1;
355 state1 <= 4'd7;
[34]356 end
[35]357 7:
[34]358 begin
[35]359 if (~usb_fifo_tx_full)
[30]360 begin
361 case (osc_byte_num)
362 1'd0: usb_fifo_tx_data <= osc_q[7:0];
363 1'd1: usb_fifo_tx_data <= osc_q[15:8];
364 endcase
[35]365 if ((&osc_byte_num) & (&osc_counter))
[30]366 begin
[35]367 state1 <= 4'd8;
[30]368 end
[35]369 else
[34]370 begin
[35]371 if (&osc_byte_num)
372 begin
373 osc_addr <= osc_addr + 10'd1;
374 osc_counter <= osc_counter + 10'd1;
375 end
376 osc_byte_num <= osc_byte_num + 1'd1;
[34]377 end
[30]378 end
379 end
[35]380 8:
[30]381 begin
[35]382 if (~usb_fifo_tx_full)
[30]383 begin
[35]384 usb_fifo_tx_wrreq <= 1'b0;
385 state1 <= 4'd1;
[30]386 end
[34]387 end
[35]388 // tst transfer
389 9:
[34]390 begin
[35]391 usb_fifo_tx_data <= tst_counter;
[34]392 usb_fifo_tx_wrreq <= 1'b1;
[35]393 tst_counter <= tst_counter + 11'd1;
394 state1 <= 4'd10;
[34]395 end
[35]396 10:
[34]397 begin
398 if (~usb_fifo_tx_full)
[30]399 begin
[35]400 usb_fifo_tx_data <= tst_counter;
401 if (tst_counter == 11'd0) //(&osc_counter)
[34]402 begin
[35]403 state1 <= 4'd11;
[34]404 end
405 else
406 begin
[35]407 tst_counter <= tst_counter + 11'd1;
[34]408 end
[30]409 end
410 end
[35]411 11:
[30]412 begin
[34]413 if (~usb_fifo_tx_full)
[30]414 begin
[34]415 usb_fifo_tx_wrreq <= 1'b0;
[35]416 state1 <= 4'd1;
[30]417 end
418 end
[35]419
420 default:
421 begin
422 state1 <= 4'd1;
423 end
[30]424 endcase
425 end
[34]426
[27]427 always @ (posedge adc_clk)
428 begin
429 case (state2)
430 1:
431 begin
432 adc_data <= 12'd0;
[35]433 state2 <= 4'd2;
[27]434 end
435
436 2:
437 begin
438 adc_data <= 12'd1024;
[35]439 state2 <= 4'd3;
[27]440 end
441
442 3:
443 begin
444 adc_data <= 12'd2048;
[35]445 state2 <= 4'd4;
[27]446 end
447
448 4:
449 begin
450 adc_data <= 12'd3072;
[35]451 state2 <= 4'd5;
[27]452 end
453
454 5:
455 begin
456 adc_data <= 12'd4095;
[35]457 state2 <= 4'd1;
[27]458 end
459
460 default:
461 begin
[35]462 state2 <= 4'd1;
[27]463 end
464 endcase
465 end
466
467endmodule
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