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source: trunk/MultiChannelUSB/Paella.v@ 39

Last change on this file since 39 was 38, checked in by demin, 15 years ago
add serial flash loader
File size: 8.7 KB

Rev	Line
[27]	1	module Paella
	2	(
	3	input wire CLK_50MHz,
	4	output wire LED,
	5
	6	inout wire [3:0] TRG,
	7	inout wire [6:0] CON_A,
	8	inout wire [15:0] CON_B,
	9	inout wire [12:0] CON_C,
	10	input wire [1:0] CON_BCLK,
	11	input wire [1:0] CON_CCLK,
	12
	13	input wire ADC_DCO,
	14	input wire ADC_FCO,
	15	input wire ADC_DB,
	16	input wire ADC_DC,
	17	input wire ADC_DD,
	18
	19	output wire USB_SLRD,
	20	output wire USB_SLWR,
	21	input wire USB_IFCLK,
	22	input wire USB_FLAGA, // EMPTY flag for EP6
	23	input wire USB_FLAGB, // FULL flag for EP8
	24	input wire USB_FLAGC,
[30]	25	inout wire USB_PA0,
	26	inout wire USB_PA1,
	27	output wire USB_PA2,
	28	inout wire USB_PA3,
	29	output wire USB_PA4,
	30	output wire USB_PA5,
	31	output wire USB_PA6,
	32	inout wire USB_PA7,
[27]	33	inout wire [7:0] USB_PB,
	34
	35	output wire RAM_CLK,
	36	output wire RAM_CE1,
	37	output wire RAM_WE,
	38	output wire [19:0] RAM_ADDR,
	39	inout wire RAM_DQAP,
	40	inout wire [7:0] RAM_DQA,
	41	inout wire RAM_DQBP,
	42	inout wire [7:0] RAM_DQB
	43	);
	44
	45	// Turn output ports off
	46	assign RAM_CLK = 1'b0;
	47	assign RAM_CE1 = 1'b0;
	48	assign RAM_WE = 1'b0;
	49	assign RAM_ADDR = 20'h00000;
	50
	51	// Turn inout ports to tri-state
	52	assign TRG = 4'bz;
	53	assign CON_A = 7'bz;
	54	assign CON_B = 16'bz;
	55	assign CON_C = 13'bz;
[30]	56	assign USB_PA0 = 1'bz;
	57	assign USB_PA1 = 1'bz;
	58	assign USB_PA3 = 1'bz;
	59	assign USB_PA7 = 1'bz;
[27]	60	assign RAM_DQAP = 1'bz;
	61	assign RAM_DQA = 8'bz;
	62	assign RAM_DQBP = 1'bz;
	63	assign RAM_DQB = 8'bz;
	64
[30]	65
	66	assign USB_PA2 = ~usb_rden;
	67	assign USB_PA4 = usb_addr[0];
	68	assign USB_PA5 = usb_addr[1];
	69	assign USB_PA6 = ~usb_pktend;
	70
[27]	71	reg [31:0] counter;
[31]	72	reg led_reg;
[30]	73	// assign LED = counter[24];
[31]	74	assign LED = led_reg;
[27]	75
	76	wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
[35]	77	wire usb_fifo_aclr;
[30]	78	reg usb_fifo_tx_wrreq;
	79	reg usb_fifo_rx_rdreq;
[27]	80	wire usb_fifo_tx_full, usb_fifo_rx_empty;
[30]	81	reg [7:0] usb_fifo_tx_data;
	82	wire [7:0] usb_fifo_rx_data;
[27]	83	wire [1:0] usb_addr;
	84
	85	assign USB_SLRD = ~usb_rdreq;
	86	assign USB_SLWR = ~usb_wrreq;
	87
	88	usb_fifo usb_fifo_unit
	89	(
	90	.usb_clk(USB_IFCLK),
	91	.usb_data(USB_PB),
	92	.usb_full(~USB_FLAGB),
	93	.usb_empty(~USB_FLAGA),
	94	.usb_wrreq(usb_wrreq),
	95	.usb_rdreq(usb_rdreq),
	96	.usb_rden(usb_rden),
	97	.usb_pktend(usb_pktend),
	98	.usb_addr(usb_addr),
[34]	99
[27]	100	.clk(CLK_50MHz),
	101	.aclr(usb_fifo_aclr),
[34]	102
	103	.tx_full(usb_fifo_tx_full),
	104	.tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
[27]	105	.tx_data(usb_fifo_tx_data),
[34]	106
[27]	107	.rx_empty(usb_fifo_rx_empty),
[37]	108	.rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
[35]	109	.rx_q(usb_fifo_rx_data)
[27]	110	);
	111
[37]	112	reg [23:0] rx_counter;
[35]	113	reg [10:0] tst_counter;
	114
	115	reg [9:0] osc_counter;
[27]	116	reg osc_reset;
[30]	117	reg osc_byte_num;
[27]	118	wire [9:0] osc_start_addr;
	119	reg [9:0] osc_addr;
	120	wire [15:0] osc_q;
	121
	122	reg hst_reset;
[30]	123	reg [1:0] hst_byte_num;
[27]	124	reg [11:0] hst_addr;
	125	wire [31:0] hst_q;
	126
[35]	127	reg [3:0] state0, state1, state2;
[27]	128	reg adc_fifo_rdreq;
	129	wire adc_fifo_rdempty;
	130	reg adc_fifo_aclr;
	131
	132	reg [31:0] adc_counter;
	133	reg adc_data_ready;
	134	wire adc_clk;
	135	reg [11:0] adc_data;
	136	wire [11:0] raw_data;
	137	wire [11:0] uwt_data;
	138	wire [1:0] uwt_flag;
	139
	140	pll pll_unit(
	141	.inclk0(CLK_50MHz),
	142	.c0(adc_clk));
	143
[38]	144	altserial_flash_loader #(
	145	.enable_shared_access("OFF"),
	146	.enhanced_mode(1),
	147	.intended_device_family("Cyclone III")) sfl_unit (
	148	.noe(1'b0),
	149	.asmi_access_granted(),
	150	.asmi_access_request(),
	151	.data0out(),
	152	.dclkin(),
	153	.scein(),
	154	.sdoin());
	155
[27]	156	adc_fifo adc_fifo_unit (
	157	.adc_clk(adc_clk),
	158	.adc_data(adc_data),
	159	.aclr(adc_fifo_aclr),
	160	.rdclk(CLK_50MHz),
	161	.rdreq(adc_fifo_rdreq),
	162	.rdempty(adc_fifo_rdempty),
	163	.raw_data(raw_data),
	164	.uwt_data({uwt_flag, uwt_data}));
	165
	166	histogram histogram_unit (
	167	.clk(CLK_50MHz),
	168	.reset(hst_reset),
	169	.data_ready(adc_data_ready),
	170	.data(raw_data),
	171	.address(hst_addr),
	172	.q(hst_q)
	173	);
	174
	175	oscilloscope oscilloscope_unit (
	176	.clk(CLK_50MHz),
	177	.reset(osc_reset),
	178	.data_ready(adc_data_ready),
	179	.raw_data(raw_data),
	180	.uwt_data(uwt_data),
	181	.threshold(16'd100),
	182	.address(osc_addr),
	183	.start_address(osc_start_addr),
	184	.q(osc_q)
	185	);
	186
[30]	187	/*
[27]	188	always @ (posedge adc_clk)
	189	begin
	190	counter <= counter + 32'd1;
	191	end
[30]	192	*/
[27]	193
	194	always @ (posedge CLK_50MHz)
	195	begin
	196	case (state0)
	197	1:
	198	begin
	199	if (~adc_fifo_rdempty)
	200	begin
[30]	201	// adc_counter <= adc_counter + 32'd1;
[27]	202	adc_fifo_rdreq <= 1'b1;
	203	adc_data_ready <= 1'b1;
[35]	204	state0 <= 4'd2;
[27]	205	end
	206	end
	207
	208	2:
	209	begin
	210	adc_fifo_rdreq <= 1'b0;
	211	adc_data_ready <= 1'b0;
[35]	212	state0 <= 4'd1;
[27]	213	end
	214
	215	default:
	216	begin
[35]	217	state0 <= 4'd1;
[27]	218	end
	219	endcase
	220	end
[35]	221
[30]	222	always @(posedge CLK_50MHz)
	223	begin
[37]	224	if (~usb_fifo_rx_empty)
	225	begin
	226	led_reg <= 1'b0;
	227	rx_counter <= 24'd0;
	228	end
	229	else
	230	begin
	231	if (&rx_counter)
	232	begin
	233	led_reg <= 1'b1;
	234	end
	235	else
	236	begin
	237	rx_counter <= rx_counter + 24'd1;
	238	end
	239	end
	240
[35]	241	case(state1)
[30]	242	1:
	243	begin
[37]	244	usb_fifo_rx_rdreq <= 1'b1;
[30]	245	usb_fifo_tx_wrreq <= 1'b0;
	246	hst_reset <= 1'b0;
	247	osc_reset <= 1'b0;
[35]	248	state1 <= 4'd2;
[30]	249	end
	250
	251	2:
	252	begin
	253	if (~usb_fifo_rx_empty)
	254	begin
	255	case (usb_fifo_rx_data)
	256	8'h30:
	257	begin
[37]	258	usb_fifo_rx_rdreq <= 1'b0;
[30]	259	hst_reset <= 1'b1;
[35]	260	state1 <= 4'd1;
[30]	261	end
	262	8'h31:
	263	begin
[37]	264	usb_fifo_rx_rdreq <= 1'b0;
[30]	265	hst_addr <= 12'd0;
	266	hst_byte_num <= 2'd0;
[35]	267	state1 <= 4'd3;
[30]	268	end
	269	8'h32:
	270	begin
[37]	271	usb_fifo_rx_rdreq <= 1'b0;
[30]	272	osc_reset <= 1'b1;
[35]	273	state1 <= 4'd1;
[30]	274	end
	275	8'h33:
	276	begin
[37]	277	usb_fifo_rx_rdreq <= 1'b0;
[30]	278	osc_addr <= osc_start_addr;
	279	osc_counter <= 10'd0;
	280	osc_byte_num <= 1'd0;
[35]	281	state1 <= 4'd6;
[30]	282	end
[35]	283	8'h34:
	284	begin
[37]	285	usb_fifo_rx_rdreq <= 1'b0;
[35]	286	state1 <= 4'd1;
	287	end
	288	8'h35:
	289	begin
[37]	290	usb_fifo_rx_rdreq <= 1'b0;
[35]	291	tst_counter <= 11'd0;
	292	state1 <= 4'd9;
	293	end
[30]	294	endcase
	295	end
	296	end
	297
[35]	298	// hst transfer
[30]	299	3:
	300	begin
[35]	301	usb_fifo_tx_data <= hst_q[7:0];
	302	usb_fifo_tx_wrreq <= 1'b1;
	303	hst_byte_num <= 2'd1;
	304	state1 <= 4'd4;
	305	end
	306	4:
	307	begin
[30]	308	if (~usb_fifo_tx_full)
	309	begin
	310	case (hst_byte_num)
	311	2'd0: usb_fifo_tx_data <= hst_q[7:0];
	312	2'd1: usb_fifo_tx_data <= hst_q[15:8];
	313	2'd2: usb_fifo_tx_data <= hst_q[23:16];
	314	2'd3: usb_fifo_tx_data <= hst_q[31:24];
	315	endcase
[34]	316	if ((&hst_byte_num) & (&hst_addr))
[30]	317	begin
[35]	318	state1 <= 4'd5;
[30]	319	end
[35]	320	else
[34]	321	begin
[35]	322	if (&hst_byte_num)
	323	begin
	324	hst_addr <= hst_addr + 12'd1;
	325	end
	326	hst_byte_num <= hst_byte_num + 2'd1;
[34]	327	end
[30]	328	end
	329	end
[34]	330	5:
	331	begin
	332	if (~usb_fifo_tx_full)
	333	begin
[35]	334	usb_fifo_tx_wrreq <= 1'b0;
	335	state1 <= 4'd1;
[34]	336	end
	337	end
	338
[35]	339	// osc transfer
[34]	340	6:
	341	begin
[35]	342	usb_fifo_tx_data <= osc_q[7:0];
	343	usb_fifo_tx_wrreq <= 1'b1;
	344	osc_byte_num <= 1'd1;
	345	state1 <= 4'd7;
[34]	346	end
[35]	347	7:
[34]	348	begin
[35]	349	if (~usb_fifo_tx_full)
[30]	350	begin
	351	case (osc_byte_num)
	352	1'd0: usb_fifo_tx_data <= osc_q[7:0];
	353	1'd1: usb_fifo_tx_data <= osc_q[15:8];
	354	endcase
[35]	355	if ((&osc_byte_num) & (&osc_counter))
[30]	356	begin
[35]	357	state1 <= 4'd8;
[30]	358	end
[35]	359	else
[34]	360	begin
[35]	361	if (&osc_byte_num)
	362	begin
	363	osc_addr <= osc_addr + 10'd1;
	364	osc_counter <= osc_counter + 10'd1;
	365	end
	366	osc_byte_num <= osc_byte_num + 1'd1;
[34]	367	end
[30]	368	end
	369	end
[35]	370	8:
[30]	371	begin
[35]	372	if (~usb_fifo_tx_full)
[30]	373	begin
[35]	374	usb_fifo_tx_wrreq <= 1'b0;
	375	state1 <= 4'd1;
[30]	376	end
[34]	377	end
[35]	378	// tst transfer
	379	9:
[34]	380	begin
[35]	381	usb_fifo_tx_data <= tst_counter;
[34]	382	usb_fifo_tx_wrreq <= 1'b1;
[35]	383	tst_counter <= tst_counter + 11'd1;
	384	state1 <= 4'd10;
[34]	385	end
[35]	386	10:
[34]	387	begin
	388	if (~usb_fifo_tx_full)
[30]	389	begin
[35]	390	usb_fifo_tx_data <= tst_counter;
	391	if (tst_counter == 11'd0) //(&osc_counter)
[34]	392	begin
[35]	393	state1 <= 4'd11;
[34]	394	end
	395	else
	396	begin
[35]	397	tst_counter <= tst_counter + 11'd1;
[34]	398	end
[30]	399	end
	400	end
[35]	401	11:
[30]	402	begin
[34]	403	if (~usb_fifo_tx_full)
[30]	404	begin
[34]	405	usb_fifo_tx_wrreq <= 1'b0;
[35]	406	state1 <= 4'd1;
[30]	407	end
	408	end
[35]	409
	410	default:
	411	begin
	412	state1 <= 4'd1;
	413	end
[30]	414	endcase
	415	end
[34]	416
[27]	417	always @ (posedge adc_clk)
	418	begin
	419	case (state2)
	420	1:
	421	begin
	422	adc_data <= 12'd0;
[35]	423	state2 <= 4'd2;
[27]	424	end
	425
	426	2:
	427	begin
	428	adc_data <= 12'd1024;
[35]	429	state2 <= 4'd3;
[27]	430	end
	431
	432	3:
	433	begin
	434	adc_data <= 12'd2048;
[35]	435	state2 <= 4'd4;
[27]	436	end
	437
	438	4:
	439	begin
	440	adc_data <= 12'd3072;
[35]	441	state2 <= 4'd5;
[27]	442	end
	443
	444	5:
	445	begin
	446	adc_data <= 12'd4095;
[35]	447	state2 <= 4'd1;
[27]	448	end
	449
	450	default:
	451	begin
[35]	452	state2 <= 4'd1;
[27]	453	end
	454	endcase
	455	end
	456
	457	endmodule

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