source: trunk/3DEES/classifier.v@ 201

Last change on this file since 201 was 190, checked in by demin, 12 years ago

classifier with parallel sum
File size: 7.6 KB
RevLine 
[180]1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
[186]7 input wire [22*width-1:0] cfg_data,
[180]8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
[190]10 output wire [6:0] out_data,
[180]11 output wire out_flag
12 );
13
[190]14 reg out_flag_reg [1:0], out_flag_next [1:0];
15 reg [8:0] out_data_reg [1:0], out_data_next [1:0];
[181]16 reg [5:0] inp_flag_reg, inp_flag_next;
[180]17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
[190]18 reg [15:0] int_pipe_reg [25:0], int_pipe_next [25:0];
[186]19 reg [2:0] int_data_reg [3:0], int_data_next [3:0];
[190]20 reg [3:0] int_temp_reg [1:0], int_temp_next [1:0];
21 reg int_flag_reg [1:0], int_flag_next [1:0];
[180]22
23 wire [width-1:0] inp_data_wire [5:0];
[190]24 wire [3:0] int_pipe_wire [6:0];
25 wire [20:0] int_comp_wire;
26
27 reg [3:0] add_data_reg [1:0], add_data_next [1:0];
28 wire [2:0] add_data_wire;
[180]29
30 integer i;
31 genvar j;
32
33 generate
34 for (j = 0; j < 6; j = j + 1)
35 begin : CLASSIFIER_INPUT_DATA
36 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
37 end
38 endgenerate
39
[190]40 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]);
41 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]);
42
43 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]);
44 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]);
[180]45 generate
46 for (j = 0; j < 4; j = j + 1)
47 begin : CLASSIFIER_COMPARTORS
[186]48 assign int_comp_wire[j*4+0+4] = (inp_data_reg[j+2] > cfg_data[(j*4+0+6)*width+width-1:(j*4+0+6)*width]);
49 assign int_comp_wire[j*4+1+4] = (inp_data_reg[j+2] > cfg_data[(j*4+1+6)*width+width-1:(j*4+1+6)*width]);
50 assign int_comp_wire[j*4+2+4] = (inp_data_reg[j+2] > cfg_data[(j*4+2+6)*width+width-1:(j*4+2+6)*width]);
51 assign int_comp_wire[j*4+3+4] = (inp_data_reg[j+2] > cfg_data[(j*4+3+6)*width+width-1:(j*4+3+6)*width]);
[183]52 end
[180]53 endgenerate
[190]54
55 assign int_comp_wire[20] = add_data_reg[1] > add_data_reg[0];
[183]56
[190]57 assign int_pipe_wire[0] = {|int_pipe_reg[3], |int_pipe_reg[2], |int_pipe_reg[1], |int_pipe_reg[0]};
[183]58
[190]59 assign int_pipe_wire[1] = {1'b0, 1'b0, |int_pipe_reg[5], |int_pipe_reg[4]};
60 assign int_pipe_wire[2] = {|int_pipe_reg[9], |int_pipe_reg[8], |int_pipe_reg[7], |int_pipe_reg[6]};
61
62 assign int_pipe_wire[3] = {|int_pipe_reg[13], |int_pipe_reg[12], |int_pipe_reg[11], |int_pipe_reg[10]};
63 assign int_pipe_wire[4] = {|int_pipe_reg[17], |int_pipe_reg[16], |int_pipe_reg[15], |int_pipe_reg[14]};
64 assign int_pipe_wire[5] = {|int_pipe_reg[21], |int_pipe_reg[20], |int_pipe_reg[19], |int_pipe_reg[18]};
65 assign int_pipe_wire[6] = {|int_pipe_reg[25], |int_pipe_reg[24], |int_pipe_reg[23], |int_pipe_reg[22]};
66
67 parallel_add #(
68 .msw_subtract("NO"),
69 .representation("UNSIGNED"),
70 .result_alignment("LSB"),
71 .shift(0),
72 .size(6),
73 .width(1),
74 .widthr(3)) parallel_add_unit (
75 .data({int_pipe_wire[2], int_pipe_wire[1][1:0]}),
76 .result(add_data_wire));
77
[180]78 always @(posedge clock)
79 begin
80 if (reset)
81 begin
[181]82 inp_flag_reg <= {(6){1'b0}};
[190]83 for (i = 0; i < 2; i = i + 1)
[183]84 begin
[190]85 out_data_reg[i] <= {(9){1'b0}};
86 out_flag_reg[i] <= {(1){1'b0}};
87 int_flag_reg[i] <= {(1){1'b0}};
88 int_temp_reg[i] <= {(4){1'b0}};
89 add_data_reg[i] <= {(3){1'b0}};
[183]90 end
[180]91 for (i = 0; i < 6; i = i + 1)
92 begin
93 inp_data_reg[i] <= {(width){1'b0}};
94 end
[190]95 for (i = 0; i < 26; i = i + 1)
[180]96 begin
97 int_pipe_reg[i] <= {(16){1'b0}};
98 end
99 for (i = 0; i < 4; i = i + 1)
100 begin
[186]101 int_data_reg[i] <= {(3){1'b0}};
[180]102 end
103 end
104 else
105 begin
[181]106 inp_flag_reg <= inp_flag_next;
[190]107 for (i = 0; i < 2; i = i + 1)
[183]108 begin
109 out_data_reg[i] <= out_data_next[i];
110 out_flag_reg[i] <= out_flag_next[i];
[190]111 int_flag_reg[i] <= int_flag_next[i];
112 int_temp_reg[i] <= int_temp_next[i];
113 add_data_reg[i] <= add_data_next[i];
[183]114 end
[180]115 for (i = 0; i < 6; i = i + 1)
116 begin
117 inp_data_reg[i] <= inp_data_next[i];
118 end
[190]119 for (i = 0; i < 26; i = i + 1)
[180]120 begin
121 int_pipe_reg[i] <= int_pipe_next[i];
122 end
123 for (i = 0; i < 4; i = i + 1)
124 begin
125 int_data_reg[i] <= int_data_next[i];
126 end
127 end
128 end
[183]129
[180]130 always @*
131 begin
[181]132 inp_flag_next = inp_flag_reg;
[190]133 for (i = 0; i < 2; i = i + 1)
[183]134 begin
135 out_data_next[i] = out_data_reg[i];
136 out_flag_next[i] = out_flag_reg[i];
[190]137 int_flag_next[i] = int_flag_reg[i];
138 int_temp_next[i] = int_temp_reg[i];
139 add_data_next[i] = add_data_reg[i];
[183]140 end
[180]141 for (i = 0; i < 6; i = i + 1)
142 begin
143 inp_data_next[i] = inp_data_reg[i];
144 end
[190]145 for (i = 0; i < 26; i = i + 1)
[180]146 begin
147 int_pipe_next[i] = int_pipe_reg[i];
148 end
149 for (i = 0; i < 4; i = i + 1)
150 begin
151 int_data_next[i] = int_data_reg[i];
152 end
153
154 if (frame)
155 begin
[181]156 inp_flag_next = inp_flag;
[180]157 for (i = 0; i < 6; i = i + 1)
158 begin
[181]159 inp_data_next[i] = inp_data_wire[i];
[180]160 end
[183]161
[190]162 if (int_flag_reg[1])
[180]163 begin
[190]164 for (i = 0; i < 2; i = i + 1)
[183]165 begin
[190]166 out_data_next[i] = {(9){1'b0}};
167 out_flag_next[i] = {(1){1'b0}};
168 int_flag_next[i] = {(1){1'b0}};
169 int_temp_next[i] = {(4){1'b0}};
170 add_data_next[i] = {(3){1'b0}};
[183]171 end
[190]172 for (i = 0; i < 26; i = i + 1)
[180]173 begin
174 int_pipe_next[i] = {(16){1'b0}};
175 end
176 end
177 else
178 begin
[190]179 out_data_next[0] = {(9){1'b0}};
180 out_data_next[1] = {out_data_reg[0][3:0], 2'd0} + out_data_reg[0][8:4];
[183]181
[190]182 out_flag_next[0] = int_flag_reg[0];
183 out_flag_next[1] = out_flag_reg[0] & int_comp_wire[20];
184
185 int_flag_next[0] = ^int_pipe_wire[1][1:0];
186 int_flag_next[1] = int_comp_wire[20];
[183]187
[190]188 add_data_next[0] = add_data_wire;
189 add_data_next[1] = add_data_reg[0];
190
[189]191 for (i = 0; i < 4; i = i + 1)
[180]192 begin
[184]193 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]};
194 end
[190]195 for (i = 4; i < 10; i = i + 1)
[184]196 begin
[190]197 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-4]};
[180]198 end
[190]199 for (i = 10; i < 26; i = i + 1)
[180]200 begin
[190]201 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
[180]202 end
203
204 for (i = 0; i < 4; i = i + 1)
205 begin
[190]206 case (int_pipe_wire[i+3][3:0])
[186]207 4'b0000: int_data_next[i] = 3'b000;
208 4'b0001: int_data_next[i] = 3'b001;
209 4'b0011: int_data_next[i] = 3'b010;
210 4'b0111: int_data_next[i] = 3'b011;
211 4'b1111: int_data_next[i] = 3'b100;
212 default: int_data_next[i] = 3'b000;
[180]213 endcase
214 end
[183]215
[190]216 int_temp_next[0] = int_pipe_wire[0];
217 int_temp_next[1] = int_pipe_wire[2];
[180]218
[190]219 case (int_temp_reg[1])
220 4'b0001: out_data_next[0][8:4] = int_data_reg[0] + 5'b00000;
221 4'b0011: out_data_next[0][8:4] = int_data_reg[1] + 5'b00101;
222 4'b0111: out_data_next[0][8:4] = int_data_reg[2] + 5'b01010;
223 4'b1111: out_data_next[0][8:4] = int_data_reg[3] + 5'b01111;
[183]224 default: out_flag_next[0] = 1'b0;
[180]225 endcase
[183]226
[190]227 case (int_temp_reg[0])
[180]228 // S1_F, electron
[190]229 4'b0001: out_data_next[0][3:0] = 4'b0000;
[183]230
[180]231 // S1_F, proton
[190]232 4'b0010: out_data_next[0][3:0] = 4'b0101;
[183]233
[180]234 // S1_S, electron
[190]235 4'b0100: out_data_next[0][3:0] = 4'b1010;
[183]236
[180]237 // S1_S, proton
[190]238 4'b1000: out_data_next[0][3:0] = 4'b1111;
[183]239
240 default: out_flag_next[0] = 1'b0;
[180]241 endcase
242 end
243 end
244 end
245
[181]246// assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
247// assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
248// assign out_data = {1'd0, int_temp_reg[0][4:0]};
[190]249 assign out_data = out_data_reg[1][6:0];
250 assign out_flag = out_flag_reg[1];
[180]251
252endmodule
Note: See TracBrowser for help on using the repository browser.