[180] | 1 | module classifier
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| 2 | #(
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| 3 | parameter width = 12 // bit width of the input data (unsigned)
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| 4 | )
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| 5 | (
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| 6 | input wire clock, frame, reset,
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[184] | 7 | input wire [18*width-1:0] cfg_data,
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[180] | 8 | input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
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| 9 | input wire [5:0] inp_flag,
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[184] | 10 | output wire [6:0] out_data,
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[180] | 11 | output wire out_flag
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| 12 | );
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| 13 |
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[183] | 14 | reg out_flag_reg [2:0], out_flag_next [2:0];
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[184] | 15 | reg [6:0] out_data_reg [2:0], out_data_next [2:0];
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[181] | 16 | reg [5:0] inp_flag_reg, inp_flag_next;
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[180] | 17 | reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
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[183] | 18 | reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
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[180] | 19 | reg [1:0] int_data_reg [3:0], int_data_next [3:0];
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[181] | 20 | reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
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[180] | 21 |
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| 22 | wire [width-1:0] inp_data_wire [5:0];
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| 23 | wire [3:0] int_pipe_wire [5:0];
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[184] | 24 | wire [15:0] int_comp_wire;
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[180] | 25 |
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| 26 | integer i;
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| 27 | genvar j;
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| 28 |
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| 29 | generate
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| 30 | for (j = 0; j < 6; j = j + 1)
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| 31 | begin : CLASSIFIER_INPUT_DATA
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| 32 | assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
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| 33 | end
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| 34 | endgenerate
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| 35 |
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| 36 | generate
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[184] | 37 | assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]);
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| 38 | assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]);
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| 39 |
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| 40 | assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]);
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| 41 | assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]);
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| 42 |
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[180] | 43 | for (j = 0; j < 4; j = j + 1)
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| 44 | begin : CLASSIFIER_COMPARTORS
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[184] | 45 | assign int_comp_wire[j*3+0+4] = (inp_data_reg[j+2] > cfg_data[(j*3+0+6)*width+width-1:(j*3+0+6)*width]);
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| 46 | assign int_comp_wire[j*3+1+4] = (inp_data_reg[j+2] > cfg_data[(j*3+1+6)*width+width-1:(j*3+1+6)*width]);
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| 47 | assign int_comp_wire[j*3+2+4] = (inp_data_reg[j+2] > cfg_data[(j*3+2+6)*width+width-1:(j*3+2+6)*width]);
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[183] | 48 | end
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[180] | 49 | endgenerate
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[183] | 50 |
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[180] | 51 | generate
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| 52 | for (j = 0; j < 4; j = j + 1)
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| 53 | begin : CLASSIFIER_PIPELINE
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| 54 | assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
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| 55 | assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
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| 56 | assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
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| 57 | assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
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| 58 | assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
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| 59 | assign int_pipe_wire[j+2][3] = 1'b0;
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| 60 | end
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| 61 | endgenerate
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[183] | 62 |
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[180] | 63 | always @(posedge clock)
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| 64 | begin
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| 65 | if (reset)
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| 66 | begin
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[181] | 67 | inp_flag_reg <= {(6){1'b0}};
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[183] | 68 | for (i = 0; i < 3; i = i + 1)
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| 69 | begin
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| 70 | out_data_reg[i] <= {(6){1'b0}};
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| 71 | out_flag_reg[i] <= 1'b0;
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| 72 | end
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[180] | 73 | for (i = 0; i < 6; i = i + 1)
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| 74 | begin
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| 75 | inp_data_reg[i] <= {(width){1'b0}};
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| 76 | end
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| 77 | for (i = 0; i < 20; i = i + 1)
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| 78 | begin
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| 79 | int_pipe_reg[i] <= {(16){1'b0}};
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| 80 | end
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| 81 | for (i = 0; i < 4; i = i + 1)
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| 82 | begin
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| 83 | int_data_reg[i] <= {(2){1'b0}};
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| 84 | end
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[181] | 85 | for (i = 0; i < 2; i = i + 1)
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| 86 | begin
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| 87 | int_temp_reg[i] <= {(5){1'b0}};
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| 88 | end
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[180] | 89 | end
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| 90 | else
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| 91 | begin
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[181] | 92 | inp_flag_reg <= inp_flag_next;
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[183] | 93 | for (i = 0; i < 3; i = i + 1)
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| 94 | begin
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| 95 | out_data_reg[i] <= out_data_next[i];
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| 96 | out_flag_reg[i] <= out_flag_next[i];
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| 97 | end
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[180] | 98 | for (i = 0; i < 6; i = i + 1)
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| 99 | begin
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| 100 | inp_data_reg[i] <= inp_data_next[i];
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| 101 | end
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| 102 | for (i = 0; i < 20; i = i + 1)
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| 103 | begin
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| 104 | int_pipe_reg[i] <= int_pipe_next[i];
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| 105 | end
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| 106 | for (i = 0; i < 4; i = i + 1)
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| 107 | begin
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| 108 | int_data_reg[i] <= int_data_next[i];
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| 109 | end
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[181] | 110 | for (i = 0; i < 2; i = i + 1)
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| 111 | begin
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| 112 | int_temp_reg[i] <= int_temp_next[i];
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| 113 | end
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[180] | 114 | end
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| 115 | end
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[183] | 116 |
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[180] | 117 | always @*
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| 118 | begin
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[181] | 119 | inp_flag_next = inp_flag_reg;
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[183] | 120 | for (i = 0; i < 3; i = i + 1)
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| 121 | begin
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| 122 | out_data_next[i] = out_data_reg[i];
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| 123 | out_flag_next[i] = out_flag_reg[i];
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| 124 | end
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[180] | 125 | for (i = 0; i < 6; i = i + 1)
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| 126 | begin
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| 127 | inp_data_next[i] = inp_data_reg[i];
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| 128 | end
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| 129 | for (i = 0; i < 20; i = i + 1)
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| 130 | begin
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| 131 | int_pipe_next[i] = int_pipe_reg[i];
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| 132 | end
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| 133 | for (i = 0; i < 4; i = i + 1)
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| 134 | begin
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| 135 | int_data_next[i] = int_data_reg[i];
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| 136 | end
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[181] | 137 | for (i = 0; i < 2; i = i + 1)
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| 138 | begin
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| 139 | int_temp_next[i] = int_temp_reg[i];
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| 140 | end
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[180] | 141 |
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| 142 | if (frame)
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| 143 | begin
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[181] | 144 | inp_flag_next = inp_flag;
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[180] | 145 | for (i = 0; i < 6; i = i + 1)
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| 146 | begin
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[181] | 147 | inp_data_next[i] = inp_data_wire[i];
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[180] | 148 | end
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[183] | 149 |
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| 150 | if (out_flag_reg[2])
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[180] | 151 | begin
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[183] | 152 | for (i = 0; i < 3; i = i + 1)
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| 153 | begin
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| 154 | out_data_next[i] = {(6){1'b0}};
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| 155 | out_flag_next[i] = 1'b0;
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| 156 | end
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[180] | 157 | for (i = 0; i < 20; i = i + 1)
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| 158 | begin
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| 159 | int_pipe_next[i] = {(16){1'b0}};
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| 160 | end
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[181] | 161 | int_temp_next[0] = {(5){1'b0}};
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| 162 | int_temp_next[1] = {(5){1'b0}};
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[180] | 163 | end
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| 164 | else
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| 165 | begin
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[183] | 166 | out_data_next[0] = {(6){1'b0}};
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| 167 | out_data_next[1] = out_data_reg[0];
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| 168 | out_data_next[2] = out_data_reg[1];
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| 169 |
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| 170 | out_flag_next[0] = 1'b1;
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| 171 | out_flag_next[1] = out_flag_reg[0];
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| 172 | out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
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| 173 |
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[184] | 174 | for (i = 0; i < 4; i = i + 1)
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[180] | 175 | begin
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[184] | 176 | int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]};
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| 177 | end
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| 178 | for (i = 4; i < 8; i = i + 1)
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| 179 | begin
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[181] | 180 | int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
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[180] | 181 | end
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| 182 | for (i = 8; i < 20; i = i + 1)
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| 183 | begin
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[184] | 184 | int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]};
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[180] | 185 | end
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| 186 |
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| 187 | for (i = 0; i < 4; i = i + 1)
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| 188 | begin
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| 189 | case (int_pipe_wire[i+2][2:0])
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[184] | 190 | 3'b000: int_data_next[i] = 2'b00;
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| 191 | 3'b001: int_data_next[i] = 2'b01;
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| 192 | 3'b011: int_data_next[i] = 2'b10;
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| 193 | 3'b111: int_data_next[i] = 2'b11;
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[180] | 194 | default: int_data_next[i] = 2'd0;
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| 195 | endcase
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| 196 | end
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[183] | 197 |
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[184] | 198 | int_temp_next[0] = {int_pipe_wire[1], ^int_pipe_wire[0]};
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[181] | 199 | int_temp_next[1] = {1'b0, int_pipe_wire[0]};
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[180] | 200 |
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[181] | 201 | case (int_temp_reg[0][4:0])
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[184] | 202 | 5'b00011: out_data_next[0][3:0] = {2'b00, int_data_next[0]};
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| 203 | 5'b00111: out_data_next[0][3:0] = {2'b01, int_data_next[1]};
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| 204 | 5'b01111: out_data_next[0][3:0] = {2'b10, int_data_next[2]};
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| 205 | 5'b11111: out_data_next[0][3:0] = {2'b11, int_data_next[3]};
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[183] | 206 | default: out_flag_next[0] = 1'b0;
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[180] | 207 | endcase
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[183] | 208 |
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[181] | 209 | case (int_temp_reg[1][3:0])
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[180] | 210 | // S1_F, electron
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[184] | 211 | 4'b0001: out_data_next[0][6:4] = 3'b100;
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[183] | 212 |
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[180] | 213 | // S1_F, proton
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[184] | 214 | 4'b0010: out_data_next[0][6:4] = 3'b101;
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[183] | 215 |
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[180] | 216 | // S1_S, electron
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[184] | 217 | 4'b0100: out_data_next[0][6:4] = 3'b110;
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[183] | 218 |
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[180] | 219 | // S1_S, proton
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[184] | 220 | 4'b1000: out_data_next[0][6:4] = 3'b111;
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[183] | 221 |
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| 222 | default: out_flag_next[0] = 1'b0;
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[180] | 223 | endcase
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| 224 | end
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| 225 | end
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| 226 | end
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| 227 |
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[181] | 228 | // assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
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| 229 | // assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
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| 230 | // assign out_data = {1'd0, int_temp_reg[0][4:0]};
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[183] | 231 | assign out_data = out_data_reg[2];
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| 232 | assign out_flag = out_flag_reg[2];
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[180] | 233 |
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| 234 | endmodule
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