[180] | 1 | module classifier
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| 2 | #(
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| 3 | parameter width = 12 // bit width of the input data (unsigned)
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| 4 | )
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| 5 | (
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| 6 | input wire clock, frame, reset,
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| 7 | input wire [14*width-1:0] cfg_data,
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| 8 | input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
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| 9 | input wire [5:0] inp_flag,
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| 10 | output wire [5:0] out_data,
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| 11 | output wire out_flag
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| 12 | );
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| 13 |
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[183] | 14 | reg out_flag_reg [2:0], out_flag_next [2:0];
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| 15 | reg [5:0] out_data_reg [2:0], out_data_next [2:0];
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[181] | 16 | reg [5:0] inp_flag_reg, inp_flag_next;
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[180] | 17 | reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
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[183] | 18 | reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
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[180] | 19 | reg [1:0] int_data_reg [3:0], int_data_next [3:0];
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[181] | 20 | reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
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[180] | 21 |
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| 22 | wire [width-1:0] inp_data_wire [5:0];
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| 23 | wire [3:0] int_pipe_wire [5:0];
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| 24 | wire [13:0] int_comp_wire;
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| 25 |
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| 26 | integer i;
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| 27 | genvar j;
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| 28 |
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| 29 | generate
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| 30 | for (j = 0; j < 6; j = j + 1)
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| 31 | begin : CLASSIFIER_INPUT_DATA
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| 32 | assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
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| 33 | end
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| 34 | endgenerate
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| 35 |
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| 36 | generate
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| 37 | assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]);
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| 38 | assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]);
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| 39 | for (j = 0; j < 4; j = j + 1)
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| 40 | begin : CLASSIFIER_COMPARTORS
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| 41 | assign int_comp_wire[j*3+0+2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);
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| 42 | assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
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| 43 | assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
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[183] | 44 | end
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[180] | 45 | endgenerate
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[183] | 46 |
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[180] | 47 | generate
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| 48 | for (j = 0; j < 4; j = j + 1)
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| 49 | begin : CLASSIFIER_PIPELINE
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| 50 | assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
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| 51 | assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
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| 52 | assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
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| 53 | assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
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| 54 | assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
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| 55 | assign int_pipe_wire[j+2][3] = 1'b0;
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| 56 | end
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| 57 | endgenerate
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[183] | 58 |
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[180] | 59 | always @(posedge clock)
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| 60 | begin
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| 61 | if (reset)
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| 62 | begin
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[181] | 63 | inp_flag_reg <= {(6){1'b0}};
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[183] | 64 | for (i = 0; i < 3; i = i + 1)
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| 65 | begin
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| 66 | out_data_reg[i] <= {(6){1'b0}};
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| 67 | out_flag_reg[i] <= 1'b0;
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| 68 | end
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[180] | 69 | for (i = 0; i < 6; i = i + 1)
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| 70 | begin
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| 71 | inp_data_reg[i] <= {(width){1'b0}};
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| 72 | end
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| 73 | for (i = 0; i < 20; i = i + 1)
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| 74 | begin
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| 75 | int_pipe_reg[i] <= {(16){1'b0}};
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| 76 | end
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| 77 | for (i = 0; i < 4; i = i + 1)
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| 78 | begin
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| 79 | int_data_reg[i] <= {(2){1'b0}};
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| 80 | end
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[181] | 81 | for (i = 0; i < 2; i = i + 1)
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| 82 | begin
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| 83 | int_temp_reg[i] <= {(5){1'b0}};
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| 84 | end
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[180] | 85 | end
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| 86 | else
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| 87 | begin
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[181] | 88 | inp_flag_reg <= inp_flag_next;
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[183] | 89 | for (i = 0; i < 3; i = i + 1)
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| 90 | begin
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| 91 | out_data_reg[i] <= out_data_next[i];
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| 92 | out_flag_reg[i] <= out_flag_next[i];
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| 93 | end
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[180] | 94 | for (i = 0; i < 6; i = i + 1)
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| 95 | begin
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| 96 | inp_data_reg[i] <= inp_data_next[i];
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| 97 | end
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| 98 | for (i = 0; i < 20; i = i + 1)
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| 99 | begin
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| 100 | int_pipe_reg[i] <= int_pipe_next[i];
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| 101 | end
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| 102 | for (i = 0; i < 4; i = i + 1)
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| 103 | begin
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| 104 | int_data_reg[i] <= int_data_next[i];
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| 105 | end
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[181] | 106 | for (i = 0; i < 2; i = i + 1)
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| 107 | begin
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| 108 | int_temp_reg[i] <= int_temp_next[i];
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| 109 | end
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[180] | 110 | end
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| 111 | end
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[183] | 112 |
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[180] | 113 | always @*
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| 114 | begin
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[181] | 115 | inp_flag_next = inp_flag_reg;
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[183] | 116 | for (i = 0; i < 3; i = i + 1)
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| 117 | begin
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| 118 | out_data_next[i] = out_data_reg[i];
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| 119 | out_flag_next[i] = out_flag_reg[i];
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| 120 | end
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[180] | 121 | for (i = 0; i < 6; i = i + 1)
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| 122 | begin
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| 123 | inp_data_next[i] = inp_data_reg[i];
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| 124 | end
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| 125 | for (i = 0; i < 20; i = i + 1)
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| 126 | begin
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| 127 | int_pipe_next[i] = int_pipe_reg[i];
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| 128 | end
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| 129 | for (i = 0; i < 4; i = i + 1)
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| 130 | begin
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| 131 | int_data_next[i] = int_data_reg[i];
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| 132 | end
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[181] | 133 | for (i = 0; i < 2; i = i + 1)
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| 134 | begin
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| 135 | int_temp_next[i] = int_temp_reg[i];
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| 136 | end
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[180] | 137 |
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| 138 | if (frame)
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| 139 | begin
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[181] | 140 | inp_flag_next = inp_flag;
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[180] | 141 | for (i = 0; i < 6; i = i + 1)
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| 142 | begin
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[181] | 143 | inp_data_next[i] = inp_data_wire[i];
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[180] | 144 | end
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[183] | 145 |
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| 146 | if (out_flag_reg[2])
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[180] | 147 | begin
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[183] | 148 | for (i = 0; i < 3; i = i + 1)
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| 149 | begin
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| 150 | out_data_next[i] = {(6){1'b0}};
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| 151 | out_flag_next[i] = 1'b0;
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| 152 | end
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[180] | 153 | for (i = 0; i < 20; i = i + 1)
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| 154 | begin
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| 155 | int_pipe_next[i] = {(16){1'b0}};
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| 156 | end
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[181] | 157 | int_temp_next[0] = {(5){1'b0}};
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| 158 | int_temp_next[1] = {(5){1'b0}};
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[180] | 159 | end
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| 160 | else
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| 161 | begin
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[183] | 162 | out_data_next[0] = {(6){1'b0}};
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| 163 | out_data_next[1] = out_data_reg[0];
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| 164 | out_data_next[2] = out_data_reg[1];
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| 165 |
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| 166 | out_flag_next[0] = 1'b1;
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| 167 | out_flag_next[1] = out_flag_reg[0];
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| 168 | out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
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| 169 |
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[180] | 170 | int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
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| 171 | int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
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| 172 | for (i = 2; i < 8; i = i + 1)
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| 173 | begin
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[181] | 174 | int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
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[180] | 175 | end
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| 176 | for (i = 8; i < 20; i = i + 1)
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| 177 | begin
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| 178 | int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
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| 179 | end
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| 180 |
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| 181 | for (i = 0; i < 4; i = i + 1)
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| 182 | begin
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| 183 | case (int_pipe_wire[i+2][2:0])
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| 184 | 3'b000: int_data_next[i] = 2'd0;
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| 185 | 3'b001: int_data_next[i] = 2'd1;
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| 186 | 3'b011: int_data_next[i] = 2'd2;
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| 187 | 3'b111: int_data_next[i] = 2'd3;
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| 188 | default: int_data_next[i] = 2'd0;
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| 189 | endcase
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| 190 | end
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[183] | 191 |
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[181] | 192 | int_temp_next[0] = {int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]};
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| 193 | int_temp_next[1] = {1'b0, int_pipe_wire[0]};
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[180] | 194 |
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[181] | 195 | case (int_temp_reg[0][4:0])
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[183] | 196 | 5'b00011: out_data_next[0][3:0] = {2'd0, int_data_next[0]};
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| 197 | 5'b00111: out_data_next[0][3:0] = {2'd1, int_data_next[1]};
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| 198 | 5'b01111: out_data_next[0][3:0] = {2'd2, int_data_next[2]};
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| 199 | 5'b11111: out_data_next[0][3:0] = {2'd3, int_data_next[3]};
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| 200 | default: out_flag_next[0] = 1'b0;
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[180] | 201 | endcase
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[183] | 202 |
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[181] | 203 | case (int_temp_reg[1][3:0])
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[180] | 204 | // S1_F, electron
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[183] | 205 | 4'b0100: out_data_next[0][5:4] = 2'd0;
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| 206 |
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[180] | 207 | // S1_F, proton
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[183] | 208 | 4'b0101: out_data_next[0][5:4] = 2'd1;
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| 209 |
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[180] | 210 | // S1_S, electron
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[183] | 211 | 4'b1000: out_data_next[0][5:4] = 2'd2;
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| 212 |
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[180] | 213 | // S1_S, proton
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[183] | 214 | 4'b1010: out_data_next[0][5:4] = 2'd3;
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| 215 |
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| 216 | default: out_flag_next[0] = 1'b0;
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[180] | 217 | endcase
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| 218 | end
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| 219 | end
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| 220 | end
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| 221 |
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[181] | 222 | // assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
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| 223 | // assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
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| 224 | // assign out_data = {1'd0, int_temp_reg[0][4:0]};
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[183] | 225 | assign out_data = out_data_reg[2];
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| 226 | assign out_flag = out_flag_reg[2];
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[180] | 227 |
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| 228 | endmodule
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