source: sandbox/MultiChannelUSB/Paella.v@ 153

Last change on this file since 153 was 149, checked in by demin, 14 years ago

add new pwm module and disable deconvolution module
File size: 11.6 KB
RevLine 
[107]1module Paella
2 (
[145]3 input wire CLK_100MHz,
[107]4 output wire LED,
5
6 input wire ADC_DCO,
7 input wire ADC_FCO,
[145]8 input wire [5:0] ADC_D,
[107]9
[149]10 output wire [3:0] PWM,
11
[145]12 output wire [1:0] SPI_SEL,
13 output wire SPI_SDO,
14 output wire SPI_CLK,
15 output wire ADC_RST,
16
17 output wire USB_SLRD,
[107]18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 output wire USB_PA2,
23 output wire USB_PA4,
24 output wire USB_PA6,
25 inout wire [7:0] USB_PB,
26
27 output wire RAM_CLK,
28 output wire RAM_WE,
[145]29 output wire [21:0] RAM_ADDR,
[107]30 inout wire RAM_DQAP,
31 inout wire [7:0] RAM_DQA,
32 inout wire RAM_DQBP,
33 inout wire [7:0] RAM_DQB
34 );
35
[145]36 localparam N = 12;
[107]37
38 // Turn output ports off
39/*
40 assign RAM_CLK = 1'b0;
41 assign RAM_CE1 = 1'b0;
42 assign RAM_WE = 1'b0;
43 assign RAM_ADDR = 20'h00000;
44*/
[145]45 assign ADC_RST = 1'b0;
46
[107]47 assign RAM_CLK = sys_clock;
48
49 assign USB_PA2 = ~usb_rden;
[145]50 assign USB_PA4 = usb_addr;
[107]51 assign USB_PA6 = ~usb_pktend;
52
53 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
54 wire usb_tx_wrreq, usb_rx_rdreq;
55 wire usb_tx_full, usb_rx_empty;
56 wire [7:0] usb_tx_data, usb_rx_data;
[145]57 wire usb_addr;
[107]58
59 assign USB_SLRD = ~usb_rdreq;
60 assign USB_SLWR = ~usb_wrreq;
61
62 usb_fifo usb_unit
63 (
64 .usb_clock(USB_IFCLK),
65 .usb_data(USB_PB),
66 .usb_full(~USB_FLAGB),
67 .usb_empty(~USB_FLAGA),
68 .usb_wrreq(usb_wrreq),
69 .usb_rdreq(usb_rdreq),
70 .usb_rden(usb_rden),
71 .usb_pktend(usb_pktend),
72 .usb_addr(usb_addr),
73
74 .clock(sys_clock),
75
76 .tx_full(usb_tx_full),
77 .tx_wrreq(usb_tx_wrreq),
78 .tx_data(usb_tx_data),
79
80 .rx_empty(usb_rx_empty),
81 .rx_rdreq(usb_rx_rdreq),
82 .rx_q(usb_rx_data)
83 );
84
85 wire [11:0] osc_mux_data [4:0];
86
87 wire [11:0] trg_mux_data;
88 wire trg_flag;
89
90 wire [2:0] coi_data;
91 wire coi_flag;
92
[145]93 wire [4*12-1:0] int_mux_data [N-1:0];
[107]94
[145]95 wire amp_flag1 [N-1:0];
96 wire [11:0] amp_data1 [N-1:0];
97
98 wire amp_flag2 [N-1:0];
99 wire [11:0] amp_data2 [N-1:0];
[107]100
101 wire cnt_good [N-1:0];
102 wire [15:0] cnt_bits_wire;
103
104 wire sys_clock, sys_frame;
105
106 wire [11:0] adc_data [N-1:0];
107 wire [11:0] sys_data [N-1:0];
108 wire [11:0] tst_data;
109
110 wire [11:0] cmp_data;
111 wire [11:0] del_data;
[63]112
[132]113 wire [20:0] cic_data [N-1:0];
[123]114
115 wire [11:0] dec_data [N-1:0];
[145]116 wire [11:0] clp_data [N-1:0];
117 wire [11:0] tmp_data [1:0];
[123]118
[107]119 wire i2c_reset;
[145]120/*
[107]121 sys_pll sys_pll_unit(
[145]122 .inclk0(CLK_100MHz),
123 .c0(sys_clock),
124 .c1(ADC_DCO),
125 .c2(ADC_FCO));
126
127 wire ADC_DCO, ADC_FCO;
128
[107]129 test test_unit(
[145]130 .clock(ADC_FCO),
[107]131 .data(tst_data));
132
133 adc_lvds #(
134 .size(3),
135 .width(12)) adc_lvds_unit (
136 .clock(sys_clock),
137 .lvds_dco(ADC_DCO),
138 .lvds_fco(ADC_FCO),
[145]139 .lvds_d(36'd0),
[107]140 .test(tst_data),
[145]141 .trig(12'd0),
[107]142 .adc_frame(sys_frame),
143 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
[145]144*/
145 sys_pll sys_pll_unit(
146 .inclk0(CLK_100MHz),
147 .c0(sys_clock));
148
149 adc_lvds #(
150 .size(6),
151 .width(24)) adc_lvds_unit (
152 .clock(sys_clock),
153 .lvds_dco(ADC_DCO),
154 .lvds_fco(ADC_FCO),
155 .lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
156 .adc_frame(sys_frame),
157 .adc_data({
158 adc_data[11], adc_data[10], adc_data[9], adc_data[8],
159 adc_data[7], adc_data[6], adc_data[5], adc_data[4],
160 adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));
[107]161
162 wire [15:0] cfg_bits [31:0];
163 wire [511:0] int_cfg_bits;
164
165 wire [39:0] cfg_mux_selector;
166
167 wire cfg_reset;
168
[145]169 wire [12:0] bus_ssel;
[107]170 wire bus_wren;
171 wire [31:0] bus_addr;
172 wire [15:0] bus_mosi;
173 wire [15:0] bus_miso [10:0];
[145]174 wire [12:0] bus_busy;
[107]175
176 wire [15:0] mrg_bus_miso;
177 wire mrg_bus_busy;
178
[145]179 wire [12*16-1:0] int_bus_miso;
[107]180
181 genvar j;
182
183 generate
184 for (j = 0; j < 32; j = j + 1)
185 begin : CONFIGURATION_OUTPUT
186 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
187 end
188 endgenerate
189
190 configuration configuration_unit (
191 .clock(sys_clock),
192 .reset(cfg_reset),
193 .bus_ssel(bus_ssel[0]),
194 .bus_wren(bus_wren),
195 .bus_addr(bus_addr[4:0]),
196 .bus_mosi(bus_mosi),
197 .bus_miso(bus_miso[0]),
198 .bus_busy(bus_busy[0]),
199 .cfg_bits(int_cfg_bits));
200
201 generate
[149]202 for (j = 0; j < 12; j = j + 1)
203 begin : MUX_DATA
[145]204 assign int_mux_data[j] = {
[149]205 amp_data2[j],
206 clp_data[j],
207 cic_data[j][19:8],
208 sys_data[j]};
[107]209 end
210 endgenerate
211
212 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
213
214 lpm_mux #(
[145]215 .lpm_size(4*12),
[107]216 .lpm_type("LPM_MUX"),
217 .lpm_width(12),
[145]218 .lpm_widths(6)) trg_mux_unit (
219 .sel(cfg_bits[4][13:8]),
220 .data({
221 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
222 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
223 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
[107]224 .result(trg_mux_data));
225
226 generate
227 for (j = 0; j < 5; j = j + 1)
228 begin : OSC_CHAIN
229
230 lpm_mux #(
[145]231 .lpm_size(4*12),
[107]232 .lpm_type("LPM_MUX"),
233 .lpm_width(12),
[145]234 .lpm_widths(6)) osc_mux_unit (
235 .sel(cfg_mux_selector[j*8+5:j*8]),
236 .data({
237 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
238 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
239 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
[107]240 .result(osc_mux_data[j]));
241 end
242 endgenerate
243
244 trigger trigger_unit (
245 .clock(sys_clock),
246 .frame(sys_frame),
247 .reset(cfg_bits[0][0]),
248 .cfg_data(cfg_bits[5][11:0]),
249 .trg_data(trg_mux_data),
250 .trg_flag(trg_flag));
251
252 oscilloscope oscilloscope_unit (
253 .clock(sys_clock),
254 .frame(sys_frame),
255 .reset(cfg_bits[0][1]),
256 .cfg_data(cfg_bits[5][12]),
257 .trg_flag(trg_flag),
258 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
259 .ram_wren(RAM_WE),
260 .ram_addr(RAM_ADDR),
261 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
262 .bus_ssel(bus_ssel[1]),
263 .bus_wren(bus_wren),
264 .bus_addr(bus_addr[19:0]),
265 .bus_mosi(bus_mosi),
266 .bus_miso(bus_miso[1]),
267 .bus_busy(bus_busy[1]));
[54]268
[145]269 new_filter #(.size(12), .width(12)) filter_unit (
[107]270 .clock(sys_clock),
[90]271 .frame(sys_frame),
[107]272 .reset(1'b0),
[145]273 .inp_data({
274 sys_data[11], sys_data[10], sys_data[9], sys_data[08],
275 sys_data[7], sys_data[6], sys_data[5], sys_data[4],
276 sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
277 .out_data({
278 cic_data[11], cic_data[10], cic_data[9], cic_data[8],
279 cic_data[7], cic_data[6], cic_data[5], cic_data[4],
280 cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));
281
282 generate
283 for (j = 0; j < 3; j = j + 1)
284 begin : DECONV_CHAIN
[149]285/*
[145]286 deconv #(.shift(22), .width(20), .widthr(12)) deconv_unit (
287 .clock(sys_clock),
288 .frame(sys_frame),
289 .reset(1'b0),
290 .del_data({6'd14, 6'd14, 6'd14, 6'd14}),
291 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
292 .tau_data({16'd16320, 16'd16320, 16'd16320, 16'd16320}),
293// .del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
294// .amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
295// .tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
296 .inp_data({
297 cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
298 cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
299 .out_data({
300 dec_data[j*4+3], dec_data[j*4+2],
301 dec_data[j*4+1], dec_data[j*4+0]}));
[149]302*/
[145]303 clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
304 .clock(sys_clock),
305 .frame(sys_frame),
306 .reset(1'b0),
[149]307 .del_data({6'd12, 6'd12, 6'd12, 6'd12}),
[145]308 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
[149]309 .tau_data({16'd16560, 16'd16560, 16'd16560, 16'd16560}), // exp(-12/240)*1024*17
[145]310 .inp_data({
311 cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
312 cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
313 .out_data({
314 clp_data[j*4+3], clp_data[j*4+2],
315 clp_data[j*4+1], clp_data[j*4+0]}));
[149]316
317/*
318 clip #(.shift(22), .width(22), .widthr(12)) clip_unit (
319 .clock(sys_clock),
320 .frame(sys_frame),
321 .reset(1'b0),
322 .del_data({6'd18, 6'd18, 6'd18, 6'd18}),
323 .amp_data({6'd5, 6'd5, 6'd5, 6'd5}),
324 .tau_data({16'd4932, 16'd4932, 16'd4932, 16'd4932}), // exp(-18/480)*1024*5
325 .inp_data({
326 cic_data[j*4+3][21:0], cic_data[j*4+2][21:0],
327 cic_data[j*4+1][21:0], cic_data[j*4+0][21:0]}),
328 .out_data({
329 clp_data[j*4+3], clp_data[j*4+2],
330 clp_data[j*4+1], clp_data[j*4+0]}));
331*/
[145]332 end
333 endgenerate
[123]334
[107]335 generate
[145]336 for (j = 0; j < 12; j = j + 1)
[107]337 begin : MCA_CHAIN
338
[145]339 assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
[149]340/*
[145]341 amplitude #(.width(12)) amplitude_unit_1 (
[123]342 .clock(sys_clock),
343 .frame(sys_frame),
[145]344 .reset(cfg_bits[0][2+j]),
345 .cfg_data({1'b0, 12'd0, 12'd5}),
346// .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
[123]347 .inp_data(dec_data[j]),
[145]348 .out_flag(amp_flag1[j]),
349 .out_data(amp_data1[j]));
[149]350*/
[145]351 amplitude #(.width(12)) amplitude_unit_2 (
[107]352 .clock(sys_clock),
353 .frame(sys_frame),
[149]354 .reset(1'b0),
[145]355 .cfg_data({1'b0, 12'd0, 12'd5}),
356// .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
357// .inp_data(dec_data[j]),
358 .inp_data(clp_data[j]),
359 .out_flag(amp_flag2[j]),
360 .out_data(amp_data2[j]));
[107]361 end
362 endgenerate
363
364 histogram32 histogram32_unit (
365 .clock(sys_clock),
366 .frame(sys_frame),
367 .reset(cfg_bits[0][5]),
[145]368 .hst_good((amp_flag1[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
369 .hst_data(amp_data1[0]),
[107]370/*
[123]371 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
[107]372 .hst_data(amp_data[j]),
373*/
374 .bus_ssel(bus_ssel[2]),
375 .bus_wren(bus_wren),
376 .bus_addr(bus_addr[12:0]),
377 .bus_mosi(bus_mosi),
378 .bus_miso(bus_miso[2]),
379 .bus_busy(bus_busy[2]));
380
381 counter hst_counter_unit (
382 .clock(sys_clock),
[145]383// .frame((sys_frame) & (~ana_dead[0])),
384 .frame(sys_frame),
[107]385 .reset(cfg_bits[0][8]),
386 .setup(cfg_bits[13][0]),
387 .count(cfg_bits[13][1]),
388 .bus_ssel(bus_ssel[5]),
389 .bus_wren(bus_wren),
390 .bus_addr(bus_addr[1:0]),
391 .bus_mosi(bus_mosi),
392 .bus_miso(bus_miso[5]),
393 .bus_busy(bus_busy[5]),
394 .cnt_good(cnt_good[0]));
395
396
397 i2c_fifo i2c_unit(
398 .clock(sys_clock),
399 .reset(i2c_reset),
400/*
401 normal connection
402 .i2c_sda(I2C_SDA),
403 .i2c_scl(I2C_SCL),
404
405 following is a cross wire connection for EPT
406*/
407 .i2c_sda(I2C_SCL),
408 .i2c_scl(I2C_SDA),
409
410 .bus_ssel(bus_ssel[11]),
411 .bus_wren(bus_wren),
412 .bus_mosi(bus_mosi),
413 .bus_busy(bus_busy[11]));
[145]414
415 spi_fifo spi_unit(
416 .clock(sys_clock),
417 .reset(1'b0),
418 .spi_sel(SPI_SEL),
419 .spi_sdo(SPI_SDO),
420 .spi_clk(SPI_CLK),
421
422 .bus_ssel(bus_ssel[12]),
423 .bus_wren(bus_wren),
424 .bus_mosi(bus_mosi),
425 .bus_busy(bus_busy[12]));
[107]426
[149]427 pwm pwm_unit(
428 .clock(sys_clock),
429 .cfg_data({cfg_bits[31], cfg_bits[30], cfg_bits[29]}),
430 .out_data(PWM));
431
[107]432 generate
433 for (j = 0; j < 11; j = j + 1)
434 begin : BUS_OUTPUT
435 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
436 end
437 endgenerate
438
439 lpm_mux #(
[145]440 .lpm_size(12),
[107]441 .lpm_type("LPM_MUX"),
442 .lpm_width(16),
443 .lpm_widths(4)) bus_miso_mux_unit (
444 .sel(bus_addr[31:28]),
445 .data(int_bus_miso),
446 .result(mrg_bus_miso));
447
448 lpm_mux #(
[145]449 .lpm_size(13),
[107]450 .lpm_type("LPM_MUX"),
451 .lpm_width(1),
452 .lpm_widths(4)) bus_busy_mux_unit (
453 .sel(bus_addr[31:28]),
454 .data(bus_busy),
455 .result(mrg_bus_busy));
456
457 lpm_decode #(
[145]458 .lpm_decodes(13),
[107]459 .lpm_type("LPM_DECODE"),
460 .lpm_width(4)) lpm_decode_unit (
461 .data(bus_addr[31:28]),
462 .eq(bus_ssel));
463
464
465 control control_unit (
466 .clock(sys_clock),
467 .rx_empty(usb_rx_empty),
468 .tx_full(usb_tx_full),
469 .rx_data(usb_rx_data),
470 .rx_rdreq(usb_rx_rdreq),
471 .tx_wrreq(usb_tx_wrreq),
472 .tx_data(usb_tx_data),
473 .bus_wren(bus_wren),
474 .bus_addr(bus_addr),
475 .bus_mosi(bus_mosi),
476 .bus_miso(mrg_bus_miso),
477 .bus_busy(mrg_bus_busy),
478 .led(LED));
479
480/*
481 altserial_flash_loader #(
482 .enable_shared_access("OFF"),
483 .enhanced_mode(1),
484 .intended_device_family("Cyclone III")) sfl_unit (
485 .noe(1'b0),
486 .asmi_access_granted(),
487 .asmi_access_request(),
488 .data0out(),
489 .dclkin(),
490 .scein(),
491 .sdoin());
492*/
493
494endmodule
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