Changeset 107 for sandbox/MultiChannelUSB/Paella.v
- Timestamp:
- Jan 17, 2011, 5:56:35 PM (14 years ago)
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- 1 edited
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sandbox/MultiChannelUSB/Paella.v
r101 r107 83 83 usb_fifo usb_unit 84 84 ( 85 .usb_cl k(USB_IFCLK),85 .usb_clock(USB_IFCLK), 86 86 .usb_data(USB_PB), 87 87 .usb_full(~USB_FLAGB), … … 93 93 .usb_addr(usb_addr), 94 94 95 .cl k(sys_clock),95 .clock(sys_clock), 96 96 97 97 .tx_full(usb_tx_full), … … 104 104 ); 105 105 106 wire [11:0] osc_mux_data [4:0]; 107 108 wire [11:0] trg_mux_data; 109 wire trg_flag; 110 111 wire [2:0] coi_data; 112 wire coi_flag; 113 114 wire [7*12-1:0] int_mux_data [N-1:0]; 115 106 116 wire ana_dead [N-1:0]; 107 117 wire ana_good [N-1:0]; … … 109 119 wire [11:0] ana_base [N-1:0]; 110 120 121 wire amp_good [N-1:0]; 122 wire [11:0] amp_data [N-1:0]; 123 111 124 wire cnt_good [N-1:0]; 112 113 wire [11:0] osc_mux_data [N-1:0]; 114 115 wire [11:0] trg_mux_data; 116 wire trg_flag; 117 118 wire [83:0] int_mux_data [N-1:0]; 125 wire [15:0] cnt_bits_wire; 119 126 120 127 wire sys_clock, sys_frame; 121 128 122 wire [11:0] adc_data [N-1:0]; 123 wire [11:0] int_data [N-1:0]; 129 wire [11:0] adc_data [N-1:0]; 124 130 wire [11:0] sys_data [N-1:0]; 131 wire [11:0] tst_data; 132 125 133 wire [11:0] cmp_data; 126 wire [11:0] nowhere;134 wire [11:0] del_data; 127 135 128 136 wire [31:0] uwt_d1 [N-1:0]; 129 137 wire [31:0] uwt_a1 [N-1:0]; 130 wire [31:0] uwt_peak1 [N-1:0];131 138 wire [31:0] uwt_d2 [N-1:0]; 132 139 wire [31:0] uwt_a2 [N-1:0]; 133 wire [31:0] uwt_peak2 [N-1:0];134 140 wire [31:0] uwt_d3 [N-1:0]; 135 141 wire [31:0] uwt_a3 [N-1:0]; 136 wire [31:0] uwt_peak3 [N-1:0];137 142 138 143 wire [1:0] uwt_flag1 [N-1:0]; … … 140 145 wire [1:0] uwt_flag3 [N-1:0]; 141 146 147 wire [11:0] cic_mux_data; 148 wire [13:0] cic_lfsr; 149 wire [24:0] cic_data1 [N-1:0]; 150 wire [24:0] cic_data2 [N-1:0]; 151 wire [24:0] cic_data3 [N-1:0]; 152 142 153 wire i2c_reset; 143 144 /*145 adc_para adc_para_unit (146 .lvds_dco(ADC_DCO),147 .lvds_fco(ADC_FCO),148 .para_good(CON_CCLK[0]),149 .para_data(CON_C[11:0]),150 .adc_data(adc_data[2]));151 */152 153 wire adc_pll_clk;154 155 /*156 adc_pll adc_pll_unit(157 .inclk0(ADC_FCO),158 .c0(adc_pll_clk));159 */160 154 161 155 sys_pll sys_pll_unit( … … 164 158 165 159 test test_unit( 166 .clk(ADC_FCO), 167 .data(adc_data[2])); 168 // .data(nowhere)); 160 .clock(ADC_FCO), 161 .data(tst_data)); 169 162 170 163 adc_lvds #( 171 164 .size(3), 172 165 .width(12)) adc_lvds_unit ( 166 .clock(sys_clock), 173 167 .lvds_dco(ADC_DCO), 174 // .lvds_dco(adc_pll_clk),175 168 .lvds_fco(ADC_FCO), 176 .lvds_d(ADC_D[2:0]), 177 // .adc_data({ adc_data[2], 178 .adc_data({ nowhere, 179 adc_data[1], 180 adc_data[0] })); 181 182 /* 183 assign cmp_data = CON_B[11:0]; 184 assign sys_clock = ADC_DCO; 185 assign sys_frame = ADC_FCO; 186 */ 169 .lvds_d(ADC_D), 170 .test(tst_data), 171 .trig({CON_B[9:0], TRG[1:0]}), 172 .adc_frame(sys_frame), 173 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]})); 187 174 188 175 wire [15:0] cfg_bits [31:0]; 189 176 wire [511:0] int_cfg_bits; 190 177 191 wire [3 1:0] cfg_mux_selector;178 wire [39:0] cfg_mux_selector; 192 179 193 180 wire cfg_reset; 194 181 195 wire [ 8:0] bus_ssel;182 wire [11:0] bus_ssel; 196 183 wire bus_wren; 197 184 wire [31:0] bus_addr; 198 185 wire [15:0] bus_mosi; 199 wire [15:0] bus_miso [ 7:0];200 wire [ 8:0] bus_busy;186 wire [15:0] bus_miso [10:0]; 187 wire [11:0] bus_busy; 201 188 202 189 wire [15:0] mrg_bus_miso; 203 190 wire mrg_bus_busy; 204 191 205 wire [1 27:0] int_bus_miso;192 wire [11*16-1:0] int_bus_miso; 206 193 207 194 genvar j; … … 229 216 begin : MUX_DATA 230 217 assign int_mux_data[j] = { 231 {ana_good[j], 11'd0}, 232 ana_data[j], 233 ana_base[j], 234 uwt_a3[j][20:9], 235 uwt_a2[j][17:6], 236 uwt_a1[j][14:3], 218 {4'd0, uwt_flag3[j][1], 7'd0}, 219 {4'd0, uwt_flag3[j][0], 7'd0}, 220 {12'd0}, 221 // {4'd0, amp_good[j], 7'd0}, 222 cic_data1[j][14:3], 223 cic_data2[j][18:7], 224 cic_data3[j][22:11], 225 // {8'd0, cic_lfsr[3:0]}, 226 // {8'd0, cic_lfsr[5:2]}, 227 // uwt_a3[j][20:9], 237 228 sys_data[j]}; 238 229 end 239 230 endgenerate 240 231 241 assign cfg_mux_selector = {cfg_bits[ 3], cfg_bits[2]};232 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]}; 242 233 243 234 lpm_mux #( 244 .lpm_size( 21),235 .lpm_size(7*3), 245 236 .lpm_type("LPM_MUX"), 246 237 .lpm_width(12), 247 238 .lpm_widths(5)) trg_mux_unit ( 248 .sel(cfg_ mux_selector[28:24]),239 .sel(cfg_bits[4][12:8]), 249 240 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}), 250 241 .result(trg_mux_data)); 251 242 252 243 generate 253 for (j = 0; j < 3; j = j + 1)244 for (j = 0; j < 5; j = j + 1) 254 245 begin : OSC_CHAIN 255 246 256 247 lpm_mux #( 257 .lpm_size( 21),248 .lpm_size(7*3), 258 249 .lpm_type("LPM_MUX"), 259 250 .lpm_width(12), … … 278 269 .frame(sys_frame), 279 270 .reset(cfg_bits[0][1]), 280 .cfg_data(cfg_bits[ 4][0]),271 .cfg_data(cfg_bits[5][12]), 281 272 .trg_flag(trg_flag), 282 .osc_data({cmp_data , osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),273 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}), 283 274 .ram_wren(RAM_WE), 284 275 .ram_addr(RAM_ADDR), … … 291 282 .bus_busy(bus_busy[1])); 292 283 293 294 adc_fifo #(.W(48)) adc_fifo_unit (295 . adc_clock(ADC_FCO),296 . adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),297 . sys_clock(sys_clock),298 . sys_frame(sys_frame),299 . sys_data({cmp_data, int_data[2], int_data[1], int_data[0]}));300 301 284 cic1 #(.size(3), .width(12)) cic3_unit ( 285 .clock(sys_clock), 286 .frame(sys_frame), 287 .reset(1'b0), 288 .inp_data({sys_data[2], sys_data[1], sys_data[0]}), 289 .out_data2({cic_data2[2], cic_data2[1], cic_data2[0]}), 290 .out_data3({cic_data3[2], cic_data3[1], cic_data3[0]}), 291 .out_data({cic_data1[2], cic_data1[1], cic_data1[0]})); 292 302 293 generate 303 294 for (j = 0; j < 3; j = j + 1) 304 295 begin : MCA_CHAIN 305 296 306 assign sys_data[j] = (cfg_bits[1][4*j]) ? ( int_data[j] ^ 12'hfff) : (int_data[j]);297 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]); 307 298 308 299 uwt_bior31 #(.L(1)) uwt_1_unit ( … … 313 304 .d(uwt_d1[j]), 314 305 .a(uwt_a1[j]), 315 .peak(uwt_peak1[j]),316 306 .flag(uwt_flag1[j])); 317 307 … … 323 313 .d(uwt_d2[j]), 324 314 .a(uwt_a2[j]), 325 .peak(uwt_peak2[j]),326 315 .flag(uwt_flag2[j])); 327 316 … … 333 322 .d(uwt_d3[j]), 334 323 .a(uwt_a3[j]), 335 .peak(uwt_peak3[j]),336 324 .flag(uwt_flag3[j])); 337 325 … … 341 329 .reset(cfg_bits[0][2+j]), 342 330 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}), 343 .uwt_flag(uwt_flag 3[j]),344 .uwt_data(uwt_ peak3[j]),331 .uwt_flag(uwt_flag2[j]), 332 .uwt_data(uwt_a2[j][17:6]), 345 333 .ana_dead(ana_dead[j]), 346 334 .ana_good(ana_good[j]), … … 348 336 .ana_base(ana_base[j])); 349 337 350 histogram histogram_unit (338 amplitude amplitude_unit ( 351 339 .clock(sys_clock), 352 340 .frame(sys_frame), 353 .reset(cfg_bits[0][5+j]), 354 .hst_good((ana_good[j]) & (cnt_good[j])), 355 .hst_data(ana_data[j]), 356 .bus_ssel(bus_ssel[2+j]), 357 .bus_wren(bus_wren), 358 .bus_addr(bus_addr[12:0]), 359 .bus_mosi(bus_mosi), 360 .bus_miso(bus_miso[2+j]), 361 .bus_busy(bus_busy[2+j])); 362 363 counter counter_unit ( 364 .clock(sys_clock), 365 .frame((sys_frame) & (~ana_dead[j])), 366 .reset(cfg_bits[0][8+j]), 367 .cfg_data(cfg_bits[12+j]), 368 .bus_ssel(bus_ssel[5+j]), 369 .bus_wren(bus_wren), 370 .bus_addr(bus_addr[1:0]), 371 .bus_mosi(bus_mosi), 372 .bus_miso(bus_miso[5+j]), 373 .bus_busy(bus_busy[5+j]), 374 .cnt_good(cnt_good[j])); 375 341 .reset(cfg_bits[0][2+j]), 342 .cfg_data(cfg_bits[12][11:0]), 343 // .cfg_data(10'd5), 344 .uwt_flag(uwt_flag3[j]), 345 .uwt_data(uwt_a3[j][20:9]), 346 .amp_good(amp_good[j]), 347 .amp_data(amp_data[j])); 376 348 end 377 349 endgenerate 350 351 histogram32 histogram32_unit ( 352 .clock(sys_clock), 353 .frame(sys_frame), 354 .reset(cfg_bits[0][5]), 355 .hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])), 356 .hst_data(ana_data[0]), 357 /* 358 .hst_good((amp_good[j]) & (cnt_good[j]) & (cfg_bits[13][1])), 359 .hst_data(amp_data[j]), 360 */ 361 .bus_ssel(bus_ssel[2]), 362 .bus_wren(bus_wren), 363 .bus_addr(bus_addr[12:0]), 364 .bus_mosi(bus_mosi), 365 .bus_miso(bus_miso[2]), 366 .bus_busy(bus_busy[2])); 367 368 counter hst_counter_unit ( 369 .clock(sys_clock), 370 .frame((sys_frame) & (~ana_dead[0])), 371 // .frame(sys_frame), 372 .reset(cfg_bits[0][8]), 373 .setup(cfg_bits[13][0]), 374 .count(cfg_bits[13][1]), 375 .bus_ssel(bus_ssel[5]), 376 .bus_wren(bus_wren), 377 .bus_addr(bus_addr[1:0]), 378 .bus_mosi(bus_mosi), 379 .bus_miso(bus_miso[5]), 380 .bus_busy(bus_busy[5]), 381 .cnt_good(cnt_good[0])); 382 378 383 379 384 i2c_fifo i2c_unit( … … 390 395 .i2c_scl(I2C_SDA), 391 396 392 .bus_ssel(bus_ssel[ 8]),393 .bus_wren(bus_wren), 394 .bus_mosi(bus_mosi), 395 .bus_busy(bus_busy[ 8]));397 .bus_ssel(bus_ssel[11]), 398 .bus_wren(bus_wren), 399 .bus_mosi(bus_mosi), 400 .bus_busy(bus_busy[11])); 396 401 397 402 generate 398 for (j = 0; j < 8; j = j + 1)403 for (j = 0; j < 11; j = j + 1) 399 404 begin : BUS_OUTPUT 400 405 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; … … 403 408 404 409 lpm_mux #( 405 .lpm_size( 8),410 .lpm_size(11), 406 411 .lpm_type("LPM_MUX"), 407 412 .lpm_width(16), 408 .lpm_widths( 3)) bus_miso_mux_unit (409 .sel(bus_addr[3 0:28]),413 .lpm_widths(4)) bus_miso_mux_unit ( 414 .sel(bus_addr[31:28]), 410 415 .data(int_bus_miso), 411 416 .result(mrg_bus_miso)); 412 417 413 418 lpm_mux #( 414 .lpm_size( 9),419 .lpm_size(12), 415 420 .lpm_type("LPM_MUX"), 416 421 .lpm_width(1), … … 420 425 .result(mrg_bus_busy)); 421 426 422 /*423 lpm_or #(424 .lpm_size(6),425 .lpm_type("LPM_OR"),426 .lpm_width(16)) bus_miso_or_unit (427 .data(int_bus_miso),428 .result(mrg_bus_miso));429 */430 431 427 lpm_decode #( 432 .lpm_decodes( 9),428 .lpm_decodes(12), 433 429 .lpm_type("LPM_DECODE"), 434 430 .lpm_width(4)) lpm_decode_unit ( 435 431 .data(bus_addr[31:28]), 436 .eq(bus_ssel), 437 .aclr(), 438 .clken(), 439 .clock(), 440 .enable()); 432 .eq(bus_ssel)); 433 441 434 442 435 control control_unit (
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