Changeset 7c7fe5e in git for modules/PdgCodeFilter.cc

Timestamp:

Jan 22, 2019, 4:21:08 PM (6 years ago)

Author:

GitHub <noreply@…>

Branches:

ImprovedOutputFile, Timing, llp, master

Children:

771843a

Parents:

d20cefb (diff), 7a86a5c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

git-author:

Pavel Demin <pavel-demin@…> (01/22/19 16:21:08)

git-committer:

GitHub <noreply@…> (01/22/19 16:21:08)

Message:

Merge pull request #65 from chekanov/master

Propogate pileup information from HepSim

File:

• modules/PdgCodeFilter.cc (modified) (2 diffs)

modules/PdgCodeFilter.cc

@@ -76 +76 @@
   fInvert = GetBool("Invert", false);
 
+  // no pileup 
+  fRequireNotPileup = GetBool("RequireNotPileup", false);
+
   fRequireStatus = GetBool("RequireStatus", false);
   fStatus = GetInt("Status", 1);
@@ -127 +130 @@
     if(fRequireStatus && (candidate->Status != fStatus)) continue;
     if(fRequireCharge && (candidate->Charge != fCharge)) continue;
+    if(fRequireNotPileup && (candidate->IsPU   >0     )) continue;
 
     pass = kTRUE;