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Changeset 5cecbc1 in git for doc/genMakefile.tcl


Ignore:
Timestamp:
Jul 24, 2015, 2:41:51 PM (9 years ago)
Author:
Michele Selvaggi <selvaggi@…>
Branches:
ImprovedOutputFile, Timing, dual_readout, llp, master
Children:
ab24890
Parents:
1343a07
Message:

fix make rules for FastJet modules

File:
1 edited

Legend:

Unmodified
Added
Removed

  • doc/genMakefile.tcl

    r1343a07 r5cecbc1  
    103103    if {$fileName == "modules/PileUpMergerPythia8.cc"} {
    104104      lappend srcObjFilesPythia8 $srcObjName$objSuf
    105     } elseif {[string match {modules/FastJet*.cc} $fileName] || [string match {modules/RunPUPPI.cc} $fileName] && $srcPrefix != {FASTJET}} {
     105    } elseif {([string match {modules/FastJet*.cc} $fileName] || [string match {modules/RunPUPPI.cc} $fileName]) && $srcPrefix != {FASTJET}} {
    106106      continue
    107107    } else {
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