- Timestamp:
- Jul 24, 2015, 2:41:51 PM (9 years ago)
- Branches:
- ImprovedOutputFile, Timing, dual_readout, llp, master
- Children:
- ab24890
- Parents:
- 1343a07
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/genMakefile.tcl
r1343a07 r5cecbc1 103 103 if {$fileName == "modules/PileUpMergerPythia8.cc"} { 104 104 lappend srcObjFilesPythia8 $srcObjName$objSuf 105 } elseif { [string match {modules/FastJet*.cc} $fileName] || [string match {modules/RunPUPPI.cc} $fileName]&& $srcPrefix != {FASTJET}} {105 } elseif {([string match {modules/FastJet*.cc} $fileName] || [string match {modules/RunPUPPI.cc} $fileName]) && $srcPrefix != {FASTJET}} { 106 106 continue 107 107 } else {
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