Timeline

Sep 23, 2009:

9:46 PM Changeset [63] by demin

add parameters for number of channels and channel resolution

9:45 PM Changeset [62] by demin

add polarity flag

9:44 PM Changeset [61] by demin

add interface for parallel ADC with unreliable clock

9:42 PM Changeset [60] by demin

interface for parallel ADC with unreliable clock

Sep 18, 2009:

1:40 PM Changeset [59] by demin

move control and test code to separate modules

1:39 PM Changeset [58] by demin

code cleanup

Sep 17, 2009:

6:39 PM Changeset [57] by demin

switch to direct instantiation of altsyncram and dcfifo

6:37 PM Changeset [56] by demin

switch to direct instantiation of altsyncram

6:37 PM Changeset [55] by demin

add pll for lvds interface

6:35 PM Changeset [54] by demin

adapat memory access to normal memory clock

6:32 PM Changeset [53] by demin

add signal invertor

6:31 PM Changeset [52] by demin

switch to normal memory clock