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Diff Rev Age Author Log Message
(edit) @155   14 years demin add one delay register
(edit) @154   14 years demin add configuration registers for the clip module
(edit) @153   14 years demin remove last empty line
(edit) @152   14 years demin add all lvds inputs
(edit) @151   14 years demin add new pwm module and add description for all clocks
(edit) @150   14 years demin add new pwm module
(edit) @149   14 years demin add new pwm module and disable deconvolution module
(edit) @148   14 years demin correctly working version
(edit) @147   14 years demin add DDIO_INPUT_REGISTER attribute
(edit) @146   14 years demin improve performance
(edit) @145   14 years demin adapt to the new card
(edit) @144   14 years demin remove size parameter and all dependent loops
(edit) @143   14 years demin add dac and adc control
(edit) @142   14 years demin adapt to the new card
(edit) @141   14 years demin multiple select pins and 24-bit data
(edit) @140   14 years demin adapt to afe8551
(edit) @139   14 years demin add signal clipping module
(edit) @138   14 years demin remove spi code
(edit) @137   14 years demin align comments
(edit) @136   14 years demin swap ep6/ep8 and reorganize usb_jtag_init
(edit) @135   14 years demin remove unused vendor commands and set auto commit length to 512
(edit) @134   14 years demin fix output assignment
(edit) @133   14 years demin reduce multiplier latency
(edit) @132   14 years demin add 4th stage to the deconvolution module
(edit) @131   14 years demin remove test outputs
(edit) @130   14 years demin add 4th stage
(edit) @129   14 years demin change width of the amplification parameter to 6-bit
(edit) @128   14 years demin add short filter with sufficient noise suppression
(edit) @127   14 years demin add back the 3 stage version of the filter with a different name
(edit) @126   14 years demin simplified 900ns version
(edit) @125   14 years demin reduce bit width of the amplification parameter
(edit) @124   14 years demin add uwt bior31 module
(edit) @123   14 years demin first more or less working version
(edit) @122   14 years demin add 4th stage
(edit) @121   14 years demin optimize timing
(edit) @120   14 years demin add shifter
(edit) @119   14 years demin replace parallel_add with lpm_add_sub
(edit) @118   14 years demin replace removed register with wire
(edit) @117   14 years demin remove unnecessary registers
(edit) @116   14 years demin fix sign conversion
(edit) @115   14 years demin add moving average module
(edit) @114   14 years demin Optimize multipliers
(edit) @113   14 years demin add deconvolution module
(edit) @112   14 years demin use usleep for jbi_delay and remove unused includes
(edit) @111   14 years demin remove unused variables and debug printouts
(edit) @110   14 years demin improve jtag i/o timing and call usb blaster functions directly from …
(edit) @109   14 years demin First working version
(edit) @108   14 years demin few minor fixes
(edit) @107   14 years demin Starting to test signal shaping algorithms
(edit) @106   14 years demin
(edit) @105   14 years demin New development directory
(edit) @104   15 years demin rename clk to clock
(edit) @103   15 years demin add fourth oscilloscope channel
(edit) @102   15 years demin initial commit
(edit) @101   15 years demin add exposure counter
(edit) @100   15 years demin multiple fixes
(edit) @99   15 years demin double the number of configuration registers
(edit) @98   15 years demin replace fixed value with parameter in the int_data_next assignment
(edit) @97   15 years demin rename several interface wires
(edit) @96   15 years demin multiple fixes
(edit) @95   15 years demin remove idle state
(edit) @94   15 years demin add exposure counter
(edit) @93   15 years demin add a few more samples
(edit) @92   15 years demin delay result by one more clock
(edit) @91   15 years demin fix communication with external SRAM
(edit) @90   15 years demin full rewrite
(edit) @89   15 years demin remove debug output
(edit) @88   15 years demin fix memory read timing
(edit) @87   15 years demin fix writing of the last EPT sample to SRAM
(edit) @86   15 years demin replace 3 ADC FIFO with one large FIFO
(edit) @85   15 years demin add possibility to record full EPT information
(edit) @84   15 years demin improve timings in all components
(edit) @83   15 years demin first working version
(edit) @82   15 years demin several minor fixes
(edit) @81   15 years demin activate all 3 ADC channels
(edit) @80   15 years demin simplify analyser interface
(edit) @79   15 years demin switch from 8 to 4 byte command
(edit) @78   15 years demin make configuration frame always visible
(edit) @77   15 years demin add configuration form and activate all channels
(edit) @76   15 years demin add counter between peaks
(edit) @75   15 years demin fix osc_mux and trg_mux
(edit) @74   15 years demin fix signal shape display configuration
(edit) @73   15 years demin first working version
(edit) @72   15 years demin testing all components together
(edit) @71   15 years demin move to central clock domain
(edit) @70   15 years demin intermediate working version with 32 bit histograms, test block and …
(edit) @69   15 years demin add I2C master
(edit) @68   15 years demin add I2C master and switch from 24 to 32 bit histogram
(edit) @67   15 years demin switch from 24 to 32 bit histogram
(edit) @66   15 years demin first working version
(edit) @65   15 years demin start testing SRAM
(edit) @64   15 years demin switch eab on
(edit) @63   15 years demin add parameters for number of channels and channel resolution
(edit) @62   15 years demin add polarity flag
(edit) @61   15 years demin add interface for parallel ADC with unreliable clock
(edit) @60   15 years demin interface for parallel ADC with unreliable clock
(edit) @59   15 years demin move control and test code to separate modules
(edit) @58   15 years demin code cleanup
(edit) @57   15 years demin switch to direct instantiation of altsyncram and dcfifo
(edit) @56   15 years demin switch to direct instantiation of altsyncram
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