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Diff Rev Age Author Log Message
(edit) @129   14 years demin change width of the amplification parameter to 6-bit
(edit) @128   14 years demin add short filter with sufficient noise suppression
(edit) @127   14 years demin add back the 3 stage version of the filter with a different name
(edit) @126   14 years demin simplified 900ns version
(edit) @125   14 years demin reduce bit width of the amplification parameter
(edit) @124   14 years demin add uwt bior31 module
(edit) @123   14 years demin first more or less working version
(edit) @122   14 years demin add 4th stage
(edit) @121   14 years demin optimize timing
(edit) @120   14 years demin add shifter
(edit) @119   14 years demin replace parallel_add with lpm_add_sub
(edit) @118   14 years demin replace removed register with wire
(edit) @117   14 years demin remove unnecessary registers
(edit) @116   14 years demin fix sign conversion
(edit) @115   14 years demin add moving average module
(edit) @114   14 years demin Optimize multipliers
(edit) @113   14 years demin add deconvolution module
(edit) @112   14 years demin use usleep for jbi_delay and remove unused includes
(edit) @111   14 years demin remove unused variables and debug printouts
(edit) @110   14 years demin improve jtag i/o timing and call usb blaster functions directly from …
(edit) @109   14 years demin First working version
(edit) @108   14 years demin few minor fixes
(edit) @107   14 years demin Starting to test signal shaping algorithms
(edit) @106   14 years demin
(edit) @105   14 years demin New development directory
(edit) @104   14 years demin rename clk to clock
(edit) @103   14 years demin add fourth oscilloscope channel
(edit) @102   14 years demin initial commit
(edit) @101   14 years demin add exposure counter
(edit) @100   14 years demin multiple fixes
(edit) @99   14 years demin double the number of configuration registers
(edit) @98   14 years demin replace fixed value with parameter in the int_data_next assignment
(edit) @97   14 years demin rename several interface wires
(edit) @96   14 years demin multiple fixes
(edit) @95   14 years demin remove idle state
(edit) @94   14 years demin add exposure counter
(edit) @93   14 years demin add a few more samples
(edit) @92   14 years demin delay result by one more clock
(edit) @91   15 years demin fix communication with external SRAM
(edit) @90   15 years demin full rewrite
(edit) @89   15 years demin remove debug output
(edit) @88   15 years demin fix memory read timing
(edit) @87   15 years demin fix writing of the last EPT sample to SRAM
(edit) @86   15 years demin replace 3 ADC FIFO with one large FIFO
(edit) @85   15 years demin add possibility to record full EPT information
(edit) @84   15 years demin improve timings in all components
(edit) @83   15 years demin first working version
(edit) @82   15 years demin several minor fixes
(edit) @81   15 years demin activate all 3 ADC channels
(edit) @80   15 years demin simplify analyser interface
(edit) @79   15 years demin switch from 8 to 4 byte command
(edit) @78   15 years demin make configuration frame always visible
(edit) @77   15 years demin add configuration form and activate all channels
(edit) @76   15 years demin add counter between peaks
(edit) @75   15 years demin fix osc_mux and trg_mux
(edit) @74   15 years demin fix signal shape display configuration
(edit) @73   15 years demin first working version
(edit) @72   15 years demin testing all components together
(edit) @71   15 years demin move to central clock domain
(edit) @70   15 years demin intermediate working version with 32 bit histograms, test block and …
(edit) @69   15 years demin add I2C master
(edit) @68   15 years demin add I2C master and switch from 24 to 32 bit histogram
(edit) @67   15 years demin switch from 24 to 32 bit histogram
(edit) @66   15 years demin first working version
(edit) @65   15 years demin start testing SRAM
(edit) @64   15 years demin switch eab on
(edit) @63   15 years demin add parameters for number of channels and channel resolution
(edit) @62   15 years demin add polarity flag
(edit) @61   15 years demin add interface for parallel ADC with unreliable clock
(edit) @60   15 years demin interface for parallel ADC with unreliable clock
(edit) @59   15 years demin move control and test code to separate modules
(edit) @58   15 years demin code cleanup
(edit) @57   15 years demin switch to direct instantiation of altsyncram and dcfifo
(edit) @56   15 years demin switch to direct instantiation of altsyncram
(edit) @55   15 years demin add pll for lvds interface
(edit) @54   15 years demin adapat memory access to normal memory clock
(edit) @53   15 years demin add signal invertor
(edit) @52   15 years demin switch to normal memory clock
(edit) @51   15 years demin first attempt to use normal memory clock
(edit) @50   15 years demin fix peak detection logic and add peak threshold
(edit) @49   15 years demin add registers for output data
(edit) @48   15 years demin cleanup test circuit
(edit) @47   15 years demin switch to direct instantiation of altsyncram
(edit) @46   15 years demin use loop for addr and reset initialisation
(edit) @45   15 years demin add fourth channel and switch from 32 to 24 bit histogram
(edit) @44   15 years demin add baseline subtraction
(edit) @43   15 years demin put back lost PIN_98 and PIN_99
(edit) @42   15 years demin code cleanup
(edit) @41   15 years demin add one real ADC channel
(edit) @40   15 years demin turn led off at startup
(edit) @39   15 years demin add configuration for EPCS16
(edit) @38   15 years demin add serial flash loader
(edit) @37   15 years demin fix communication with fifo_rx_unit
(edit) @36   15 years demin several minor fixes
(edit) @35   15 years demin first working version
(edit) @34   15 years demin working test version
(edit) @33   15 years demin return to simple USB interface with some adjustments
(edit) @32   15 years demin change LED polarity
(edit) @31   15 years demin attemp to improve USB interface
(edit) @30   15 years demin put all components in place
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