Changeset 31 for trunk/MultiChannelUSB/usb_fifo.v
- Timestamp:
- Sep 4, 2009, 10:16:52 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/usb_fifo.v
r30 r31 11 11 input wire [7:0] tx_data, 12 12 output wire tx_full, rx_empty, 13 output wire [7:0] rx_data 13 output wire [7:0] rx_data, 14 output wire led 14 15 ); 15 16 16 17 // bidirectional data bus 17 wire usb_wren;18 wire [7:0] usb_datain = usb_data;19 wire [7:0] usb_dataout;18 reg int_addr, int_wren, int_rden, int_wrreq, int_rdreq; 19 wire [7:0] int_datain = usb_data; 20 wire [7:0] int_dataout; 20 21 21 assign usb_data = usb_wren ? usb_dataout : 8'bz;22 assign usb_data = int_wren ? int_dataout : 8'bz; 22 23 23 24 wire rx_full, tx_empty; 25 wire rx_ready, tx_ready; 24 26 reg [8:0] byte_counter; 25 27 reg [4:0] idle_counter; 28 29 assign led = ~usb_empty; 26 30 27 31 fifo32x8 fifo_tx_unit ( … … 29 33 .data(tx_data), 30 34 .rdclk(usb_clk), 31 .rdreq( usb_wrreq),35 .rdreq(int_wrreq), 32 36 .wrclk(clk), 33 37 .wrreq(tx_wrreq), 34 .q( usb_dataout),38 .q(int_dataout), 35 39 .rdempty(tx_empty), 36 40 .wrfull(tx_full)); … … 38 42 fifo32x8 fifo_rx_unit ( 39 43 .aclr(aclr), 40 .data( usb_datain),44 .data(int_datain), 41 45 .rdclk(clk), 42 46 .rdreq(rx_rdreq), 43 47 .wrclk(usb_clk), 44 .wrreq( usb_rdreq),48 .wrreq(int_rdreq), 45 49 .q(rx_data), 46 50 .rdempty(rx_empty), 47 51 .wrfull(rx_full)); 52 53 assign rx_ready = (~usb_empty) & (~rx_full); 54 assign tx_ready = (~usb_full) & (~tx_empty); 48 55 49 56 always @ (posedge usb_clk) 50 57 begin 58 casez ({rx_ready, tx_ready, int_addr, int_rden}) 59 4'b00??: // idle 60 begin 61 int_addr <= 1'b0; 62 int_rden <= 1'b0; 63 int_wren <= 1'b0; 64 int_rdreq <= 1'b0; 65 int_wrreq <= 1'b0; 66 end 67 4'b1?1?: // set read addr 68 begin 69 int_addr <= 1'b0; 70 int_rden <= 1'b0; 71 int_wren <= 1'b0; 72 int_rdreq <= 1'b0; 73 int_wrreq <= 1'b0; 74 end 75 4'b1?00: // enable reads 76 begin 77 int_addr <= 1'b0; 78 int_rden <= 1'b1; 79 int_wren <= 1'b0; 80 int_rdreq <= 1'b0; 81 int_wrreq <= 1'b0; 82 end 83 4'b1?01: // read 84 begin 85 int_addr <= 1'b0; 86 int_rden <= 1'b1; 87 int_wren <= 1'b0; 88 int_rdreq <= 1'b1; 89 int_wrreq <= 1'b0; 90 end 91 4'b0101: // disable reads 92 begin 93 int_addr <= 1'b0; 94 int_rden <= 1'b0; 95 int_wren <= 1'b0; 96 int_rdreq <= 1'b0; 97 int_wrreq <= 1'b0; 98 end 99 4'b0100: // set write addr 100 begin 101 int_addr <= 1'b1; 102 int_rden <= 1'b0; 103 int_wren <= 1'b1; 104 int_rdreq <= 1'b0; 105 int_wrreq <= 1'b0; 106 end 107 4'b011?: // write 108 begin 109 int_addr <= 1'b1; 110 int_rden <= 1'b0; 111 int_wren <= 1'b1; 112 int_rdreq <= 1'b0; 113 int_wrreq <= 1'b1; 114 end 115 endcase 116 /* 51 117 if (usb_pktend) 52 118 begin … … 64 130 idle_counter <= idle_counter + 5'd1; 65 131 end 132 */ 66 133 end 67 134 68 assign usb_pktend = (&idle_counter); 69 // assign usb_pktend = 1'b0; 70 assign usb_rdreq = (~usb_empty) & (~rx_full); 71 assign usb_wrreq = (~usb_rdreq) & (~usb_full) & (~tx_empty); 72 assign usb_rden = usb_rdreq; 73 assign usb_wren = usb_wrreq; 74 assign usb_addr = usb_empty ? 2'b11 : 2'b10; 135 assign usb_addr = {1'b1, int_addr}; 136 assign usb_rden = int_rden; 137 assign usb_rdreq = int_rdreq; 138 assign usb_wrreq = int_wrreq; 139 // assign usb_pktend = (&idle_counter); 140 assign usb_pktend = 1'b0; 75 141 76 142 endmodule
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