1 | module usb_fifo
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2 | (
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3 | input wire usb_clk,
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4 | inout wire [7:0] usb_data,
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5 | input wire usb_full, usb_empty,
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6 | output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
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7 | output wire [1:0] usb_addr,
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8 |
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9 | input wire clk, aclr,
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10 | input wire tx_wrreq, rx_rdreq,
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11 | input wire [7:0] tx_data,
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12 | output wire tx_full, rx_empty,
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13 | output wire [7:0] rx_data
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14 | );
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15 |
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16 | // bidirectional data bus
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17 | wire usb_wren;
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18 | wire [7:0] usb_datain = usb_data;
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19 | wire [7:0] usb_dataout;
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20 |
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21 | assign usb_data = usb_wren ? usb_dataout : 8'bz;
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22 |
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23 | wire rx_full, tx_empty;
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24 | reg [8:0] byte_counter;
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25 | reg [4:0] idle_counter;
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26 |
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27 | fifo32x8 fifo_tx_unit (
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28 | .aclr(aclr),
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29 | .data(tx_data),
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30 | .rdclk(usb_clk),
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31 | .rdreq(usb_wrreq),
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32 | .wrclk(clk),
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33 | .wrreq(tx_wrreq),
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34 | .q(usb_dataout),
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35 | .rdempty(tx_empty),
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36 | .wrfull(tx_full));
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37 |
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38 | fifo32x8 fifo_rx_unit (
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39 | .aclr(aclr),
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40 | .data(usb_datain),
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41 | .rdclk(clk),
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42 | .rdreq(rx_rdreq),
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43 | .wrclk(usb_clk),
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44 | .wrreq(usb_rdreq),
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45 | .q(rx_data),
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46 | .rdempty(rx_empty),
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47 | .wrfull(rx_full));
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48 |
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49 | always @ (posedge usb_clk)
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50 | begin
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51 | if (usb_pktend)
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52 | begin
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53 | byte_counter <= 9'd0;
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54 | idle_counter <= 5'd0;
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55 | end
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56 | else if (usb_wrreq)
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57 | begin
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58 | byte_counter <= byte_counter + 9'd1;
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59 | idle_counter <= 5'd0;
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60 | end
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61 | else if ((|byte_counter) & (tx_empty))
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62 | begin
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63 | byte_counter <= byte_counter;
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64 | idle_counter <= idle_counter + 5'd1;
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65 | end
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66 | end
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67 |
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68 | assign usb_pktend = (&idle_counter);
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69 | // assign usb_pktend = 1'b0;
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70 | assign usb_rdreq = (~usb_empty) & (~rx_full);
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71 | assign usb_wrreq = (~usb_rdreq) & (~usb_full) & (~tx_empty);
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72 | assign usb_rden = usb_rdreq;
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73 | assign usb_wren = usb_wrreq;
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74 | assign usb_addr = usb_empty ? 2'b11 : 2'b10;
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75 |
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76 | endmodule
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