source: trunk/MultiChannelUSB/usb_fifo.v@ 30

Last change on this file since 30 was 30, checked in by demin, 15 years ago

put all components in place

File size: 1.7 KB
Line 
1module usb_fifo
2 (
3 input wire usb_clk,
4 inout wire [7:0] usb_data,
5 input wire usb_full, usb_empty,
6 output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
7 output wire [1:0] usb_addr,
8
9 input wire clk, aclr,
10 input wire tx_wrreq, rx_rdreq,
11 input wire [7:0] tx_data,
12 output wire tx_full, rx_empty,
13 output wire [7:0] rx_data
14 );
15
16 // bidirectional data bus
17 wire usb_wren;
18 wire [7:0] usb_datain = usb_data;
19 wire [7:0] usb_dataout;
20
21 assign usb_data = usb_wren ? usb_dataout : 8'bz;
22
23 wire rx_full, tx_empty;
24 reg [8:0] byte_counter;
25 reg [4:0] idle_counter;
26
27 fifo32x8 fifo_tx_unit (
28 .aclr(aclr),
29 .data(tx_data),
30 .rdclk(usb_clk),
31 .rdreq(usb_wrreq),
32 .wrclk(clk),
33 .wrreq(tx_wrreq),
34 .q(usb_dataout),
35 .rdempty(tx_empty),
36 .wrfull(tx_full));
37
38 fifo32x8 fifo_rx_unit (
39 .aclr(aclr),
40 .data(usb_datain),
41 .rdclk(clk),
42 .rdreq(rx_rdreq),
43 .wrclk(usb_clk),
44 .wrreq(usb_rdreq),
45 .q(rx_data),
46 .rdempty(rx_empty),
47 .wrfull(rx_full));
48
49 always @ (posedge usb_clk)
50 begin
51 if (usb_pktend)
52 begin
53 byte_counter <= 9'd0;
54 idle_counter <= 5'd0;
55 end
56 else if (usb_wrreq)
57 begin
58 byte_counter <= byte_counter + 9'd1;
59 idle_counter <= 5'd0;
60 end
61 else if ((|byte_counter) & (tx_empty))
62 begin
63 byte_counter <= byte_counter;
64 idle_counter <= idle_counter + 5'd1;
65 end
66 end
67
68 assign usb_pktend = (&idle_counter);
69// assign usb_pktend = 1'b0;
70 assign usb_rdreq = (~usb_empty) & (~rx_full);
71 assign usb_wrreq = (~usb_rdreq) & (~usb_full) & (~tx_empty);
72 assign usb_rden = usb_rdreq;
73 assign usb_wren = usb_wrreq;
74 assign usb_addr = usb_empty ? 2'b11 : 2'b10;
75
76endmodule
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