Changeset 186 for trunk/3DEES/histogram32.v

Timestamp:

Mar 18, 2014, 3:10:11 PM (11 years ago)

Author:

demin

Message:

add fifth bin

File:

• trunk/3DEES/histogram32.v (modified) (7 diffs)

trunk/3DEES/histogram32.v

@@ -4 +4 @@
                 
                 input   wire                    hst_good,
-                input   wire    [5:0]  hst_data,
+                input   wire    [6:0]   hst_data,
 
                 input   wire                    bus_ssel, bus_wren,
@@ -17 +17 @@
         reg             [3:0]   int_case_reg, int_case_next;
         reg                             int_wren_reg, int_wren_next;
-        reg             [5:0]   int_addr_reg, int_addr_next;
+        reg             [6:0]   int_addr_reg, int_addr_next;
         reg             [31:0]  int_data_reg, int_data_next;
 
@@ -38 +38 @@
                 .intended_device_family("Cyclone III"),
                 .lpm_type("altsyncram"),
-                .numwords_a(64),
-                .numwords_b(128),
+                .numwords_a(80),
+                .numwords_b(160),
                 .operation_mode("BIDIR_DUAL_PORT"),
                 .outdata_aclr_a("NONE"),
@@ -49 +49 @@
                 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
                 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
-                .widthad_a(6),
-                .widthad_b(7),
+                .widthad_a(7),
+                .widthad_b(8),
                 .width_a(32),
                 .width_b(16),
@@ -86 +86 @@
         begin
                         int_wren_reg <= 1'b1;
-                        int_addr_reg <= 6'd0;
+                        int_addr_reg <= 7'd0;
                         int_data_reg <= 32'd0;
                         int_case_reg <= 4'b0;
@@ -139 +139 @@
                         begin
                                 // write zeros
-                                int_addr_next = int_addr_reg + 6'd1;
+                                int_addr_next = int_addr_reg + 7'd1;
                                 if (&int_addr_reg)
                                 begin
@@ -187 +187 @@
                         begin
                                 int_wren_next = 1'b0;
-                                int_addr_next = 6'd0;
+                                int_addr_next = 7'd0;
                                 int_data_next = 32'd0;
                                 int_case_next = 4'd0;