Changeset 180 for trunk/3DEES/histogram32.v

Timestamp:

Jan 15, 2014, 1:30:27 AM (12 years ago)

Author:

demin

Message:

add classifier and remove unneeded modules

File:

• trunk/3DEES/histogram32.v (modified) (7 diffs)

trunk/3DEES/histogram32.v

@@ -4 +4 @@
                 
                 input   wire                    hst_good,
-                input   wire    [11:0]  hst_data,
+                input   wire    [5:0]  hst_data,
 
                 input   wire                    bus_ssel, bus_wren,
-                input   wire    [12:0]  bus_addr,
+                input   wire    [6:0]   bus_addr,
                 input   wire    [15:0]  bus_mosi,
 
@@ -17 +17 @@
         reg             [3:0]   int_case_reg, int_case_next;
         reg                             int_wren_reg, int_wren_next;
-        reg             [11:0]  int_addr_reg, int_addr_next;
+        reg             [5:0]   int_addr_reg, int_addr_next;
         reg             [31:0]  int_data_reg, int_data_next;
 
-        reg             [12:0]  bus_addr_reg, bus_addr_next;
+        reg             [6:0]   bus_addr_reg, bus_addr_next;
         reg             [15:0]  bus_miso_reg, bus_miso_next;
 
@@ -38 +38 @@
                 .intended_device_family("Cyclone III"),
                 .lpm_type("altsyncram"),
-                .numwords_a(4096),
-                .numwords_b(8192),
+                .numwords_a(64),
+                .numwords_b(128),
                 .operation_mode("BIDIR_DUAL_PORT"),
                 .outdata_aclr_a("NONE"),
@@ -49 +49 @@
                 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
                 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
-                .widthad_a(12),
-                .widthad_b(13),
+                .widthad_a(6),
+                .widthad_b(7),
                 .width_a(32),
                 .width_b(16),
@@ -86 +86 @@
         begin
                         int_wren_reg <= 1'b1;
-                        int_addr_reg <= 12'd0;
+                        int_addr_reg <= 6'd0;
                         int_data_reg <= 32'd0;
                         int_case_reg <= 4'b0;
-                        bus_addr_reg <= 13'd0;
+                        bus_addr_reg <= 7'd0;
                         bus_miso_reg <= 16'd0;
                         bus_wren_reg <= 1'b0;
@@ -139 +139 @@
                         begin
                                 // write zeros
-                                int_addr_next = int_addr_reg + 12'd1;
+                                int_addr_next = int_addr_reg + 6'd1;
                                 if (&int_addr_reg)
                                 begin
@@ -187 +187 @@
                         begin
                                 int_wren_next = 1'b0;
-                                int_addr_next = 12'd0;
+                                int_addr_next = 6'd0;
                                 int_data_next = 32'd0;
                                 int_case_next = 4'd0;