Changeset 180 for trunk/3DEES/histogram32.v
- Timestamp:
- Jan 15, 2014, 1:30:27 AM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/histogram32.v
r107 r180 4 4 5 5 input wire hst_good, 6 input wire [ 11:0] hst_data,6 input wire [5:0] hst_data, 7 7 8 8 input wire bus_ssel, bus_wren, 9 input wire [ 12:0] bus_addr,9 input wire [6:0] bus_addr, 10 10 input wire [15:0] bus_mosi, 11 11 … … 17 17 reg [3:0] int_case_reg, int_case_next; 18 18 reg int_wren_reg, int_wren_next; 19 reg [ 11:0] int_addr_reg, int_addr_next;19 reg [5:0] int_addr_reg, int_addr_next; 20 20 reg [31:0] int_data_reg, int_data_next; 21 21 22 reg [ 12:0] bus_addr_reg, bus_addr_next;22 reg [6:0] bus_addr_reg, bus_addr_next; 23 23 reg [15:0] bus_miso_reg, bus_miso_next; 24 24 … … 38 38 .intended_device_family("Cyclone III"), 39 39 .lpm_type("altsyncram"), 40 .numwords_a( 4096),41 .numwords_b( 8192),40 .numwords_a(64), 41 .numwords_b(128), 42 42 .operation_mode("BIDIR_DUAL_PORT"), 43 43 .outdata_aclr_a("NONE"), … … 49 49 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), 50 50 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), 51 .widthad_a( 12),52 .widthad_b( 13),51 .widthad_a(6), 52 .widthad_b(7), 53 53 .width_a(32), 54 54 .width_b(16), … … 86 86 begin 87 87 int_wren_reg <= 1'b1; 88 int_addr_reg <= 12'd0;88 int_addr_reg <= 6'd0; 89 89 int_data_reg <= 32'd0; 90 90 int_case_reg <= 4'b0; 91 bus_addr_reg <= 13'd0;91 bus_addr_reg <= 7'd0; 92 92 bus_miso_reg <= 16'd0; 93 93 bus_wren_reg <= 1'b0; … … 139 139 begin 140 140 // write zeros 141 int_addr_next = int_addr_reg + 12'd1;141 int_addr_next = int_addr_reg + 6'd1; 142 142 if (&int_addr_reg) 143 143 begin … … 187 187 begin 188 188 int_wren_next = 1'b0; 189 int_addr_next = 12'd0;189 int_addr_next = 6'd0; 190 190 int_data_next = 32'd0; 191 191 int_case_next = 4'd0;
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