- Timestamp:
- Mar 18, 2014, 3:10:11 PM (10 years ago)
- Location:
- trunk/3DEES
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/3DEES/Paella.v
r185 r186 94 94 95 95 wire cls_flag; 96 wire [ 6:0] cls_data;96 wire [7:0] cls_data; 97 97 98 98 wire [1:0] amp_mux_flag [2:0]; … … 200 200 assign int_mux_data[j] = { 201 201 {4'd0, cls_flag, 7'd0}, 202 { 5'd0, cls_data},202 {4'd0, cls_data}, 203 203 {4'd0, amp_flag[j][0], 7'd0}, 204 204 amp_data[j][11:0], … … 292 292 .reset(1'b0), 293 293 // .del_data({6'd0, 6'd32, 6'd32, 6'd32}), 294 .del_data({6'd0, cfg_bits[ 39+6*j][5:0], cfg_bits[37+6*j][5:0], cfg_bits[35+6*j][5:0]}),294 .del_data({6'd0, cfg_bits[41+6*j][5:0], cfg_bits[39+6*j][5:0], cfg_bits[37+6*j][5:0]}), 295 295 .amp_data({6'd0, 6'd20, 6'd20, 6'd20}), 296 296 // .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}), 297 297 // exp(-32/1000)*1024*20 298 .tau_data({16'd0, cfg_bits[ 38+6*j], cfg_bits[36+6*j], cfg_bits[34+6*j]}),298 .tau_data({16'd0, cfg_bits[40+6*j], cfg_bits[38+6*j], cfg_bits[36+6*j]}), 299 299 .inp_data({ 300 300 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}), … … 341 341 // 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}), 342 342 .cfg_data({cfg_bits[33][11:0], cfg_bits[32][11:0], 343 cfg_bits[35][11:0], cfg_bits[34][11:0], cfg_bits[33][11:0], cfg_bits[32][11:0], 343 344 cfg_bits[31][11:0], cfg_bits[30][11:0], cfg_bits[29][11:0], cfg_bits[28][11:0], 344 345 cfg_bits[27][11:0], cfg_bits[26][11:0], cfg_bits[25][11:0], cfg_bits[24][11:0], … … 357 358 .reset(cfg_bits[0][5]), 358 359 .hst_good(cls_flag & cfg_bits[6][0]), 359 .hst_data(cls_data[ 5:0]),360 .hst_data(cls_data[6:0]), 360 361 .bus_ssel(bus_ssel[2]), 361 362 .bus_wren(bus_wren), 362 .bus_addr(bus_addr[ 6:0]),363 .bus_addr(bus_addr[7:0]), 363 364 .bus_mosi(bus_mosi), 364 365 .bus_miso(bus_miso[2]), -
trunk/3DEES/UserInterface.tcl
r184 r186 56 56 {3_2} 13 57 57 {3_3} 14 58 {3_4} 15 58 59 {4_0} 3 59 {4_1} 15 60 {4_2} 16 61 {4_3} 17 60 {4_1} 16 61 {4_2} 17 62 {4_3} 18 63 {4_4} 19 62 64 {5_0} 4 63 {5_1} 18 64 {5_2} 19 65 {5_3} 20 65 {5_1} 20 66 {5_2} 21 67 {5_3} 22 68 {5_4} 23 66 69 {6_0} 5 67 {6_1} 21 68 {6_2} 22 69 {6_3} 23 70 {6_1} 24 71 {6_2} 25 72 {6_3} 26 73 {6_4} 27 70 74 } 71 75 # ------------------------------------------------------------------------- … … 82 86 11 3000 83 87 2 10 84 12 31 85 13 52 86 14 79 87 3 60 88 15 135 89 16 171 90 17 233 91 4 249 92 18 348 93 19 495 94 20 693 95 5 505 96 21 606 97 22 707 98 23 808 99 } 100 101 88 12 10 89 13 31 90 14 52 91 15 79 92 3 10 93 16 60 94 17 135 95 18 171 96 19 233 97 4 10 98 20 249 99 21 348 100 22 495 101 23 693 102 5 10 103 24 505 104 25 606 105 26 707 106 27 808 107 } 108 109 102 110 # ------------------------------------------------------------------------- 103 111 … … 109 117 3 {af} 110 118 4 {bn} 119 5 {bf} 111 120 } 112 121 … … 328 337 trace add variable [myvar delay] write [myproc delay_update] 329 338 trace add variable [myvar thrs] write [myproc thrs_update] 330 339 331 340 my delay_update 332 341 my thrs_update … … 342 351 343 352 set thrs [frame ${master}.thrs] 353 set bins [frame ${master}.bins] 344 354 set clip [frame ${master}.clip] 345 355 … … 347 357 348 358 set column 0 349 foreach {input} [list "ADC" " thrs 1" "thrs 2" "thrs 3" "thrs 4"] {359 foreach {input} [list "ADC" "e thrs min" "e thrs max" "p thrs min" "p thrs max"] { 350 360 label ${config(thrs)}.label_${column} -text "${input}" 351 361 grid ${config(thrs)}.label_${column} -row 0 -column ${column} -sticky ew -padx 5 -pady 7 … … 353 363 } 354 364 355 foreach {ch id} [array get adcCodes ] {365 foreach {ch id} [array get adcCodes {[1-2]}] { 356 366 label ${config(thrs)}.chan_${ch} -text "${id} " 357 367 grid ${config(thrs)}.chan_${ch} -row ${ch} -column 0 -sticky ew -padx 5 -pady 7 … … 367 377 368 378 grid $config(thrs) -row 0 -column 0 -sticky news -padx 10 379 380 set config(bins) [labelframe ${bins}.frame -borderwidth 1 -relief sunken -text {Bins}] 381 382 set column 0 383 foreach {input} [list "ADC" "thrs 0" "thrs 1" "thrs 2" "thrs 3" "thrs 4"] { 384 label ${config(bins)}.label_${column} -text "${input}" 385 grid ${config(bins)}.label_${column} -row 0 -column ${column} -sticky ew -padx 5 -pady 7 386 incr column 387 } 388 389 foreach {ch id} [array get adcCodes {[3-6]}] { 390 label ${config(bins)}.chan_${ch} -text "${id} " 391 grid ${config(bins)}.chan_${ch} -row ${ch} -column 0 -sticky ew -padx 5 -pady 7 392 foreach {num} [list 0 1 2 3 4] { 393 set column [expr {$num + 1}] 394 set value $cfgCodes(${ch}_${num}) 395 spinbox ${config(bins)}.bins_${value} -from 0 -to 4095 \ 396 -increment 10 -width 10 -textvariable [myvar thrs($value)] \ 397 -validate all -vcmd {::mca::validate 4095 4 %P} 398 grid ${config(bins)}.bins_${value} -row ${ch} -column ${column} -sticky w -padx 5 -pady 7 399 } 400 } 401 402 grid $config(bins) -row 0 -column 0 -sticky news -padx 10 369 403 370 404 set config(clip) [labelframe ${clip}.frame -borderwidth 1 -relief sunken -text {Signal clipping}] … … 392 426 grid $config(clip) -row 0 -column 0 -sticky news -padx 10 393 427 394 grid ${thrs} -row 0 -column 1 -sticky news 428 grid ${thrs} -row 0 -column 2 -sticky news 429 grid ${bins} -row 0 -column 1 -sticky news 395 430 grid ${clip} -row 0 -column 0 -sticky news 396 431 397 432 grid columnconfigure ${master} 0 -weight 1 398 433 grid columnconfigure ${master} 1 -weight 1 434 grid columnconfigure ${master} 2 -weight 1 399 435 grid rowconfigure ${master} 0 -weight 1 400 436 401 437 grid rowconfigure ${thrs} 0 -weight 0 438 grid rowconfigure ${bins} 0 -weight 0 402 439 grid rowconfigure ${clip} 0 -weight 0 403 440 } … … 413 450 set b $decay($i).0 414 451 set value [expr int(exp(-${a}/${b})*1024*20)] 415 append command [format {000200%02x0004%04x} [expr {3 4+ 2 * (${i} - 1)}] $value]452 append command [format {000200%02x0004%04x} [expr {36 + 2 * (${i} - 1)}] $value] 416 453 } 417 454 … … 440 477 441 478 set command {} 442 for {set i 0} {$i <= 2 3} {incr i} {479 for {set i 0} {$i <= 27} {incr i} { 443 480 append command [format {000200%02x0004%04x} [expr {10 + ${i}}] $thrs($i)] 444 481 } … … 639 676 my set data {} 640 677 641 vector create [myvar xvec]( 64)642 vector create [myvar yvec]( 64)643 644 # fill one vector for the x axis with 64points645 [myvar xvec] seq -0.5 63.5678 vector create [myvar xvec](80) 679 vector create [myvar yvec](80) 680 681 # fill one vector for the x axis with 80 points 682 [myvar xvec] seq -0.5 79.5 646 683 647 684 my setup … … 684 721 $graph grid configure -hide no 685 722 $graph legend configure -hide yes 686 $graph axis configure x -min 0 -max 64723 $graph axis configure x -min 0 -max 80 687 724 688 725 set config [frame ${master}.config -width 170] … … 845 882 my instvar controller config number 846 883 847 set size 64884 set size 80 848 885 849 886 set prefix [format {%x} [expr {$number + 2}]] … … 892 929 893 930 HstDisplay instproc register {} { 894 my save_data [join [[myvar yvec] range 0 63] \n]931 my save_data [join [[myvar yvec] range 0 79] \n] 895 932 } 896 933 -
trunk/3DEES/classifier.v
r184 r186 5 5 ( 6 6 input wire clock, frame, reset, 7 input wire [ 18*width-1:0] cfg_data,7 input wire [22*width-1:0] cfg_data, 8 8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F} 9 9 input wire [5:0] inp_flag, 10 output wire [ 6:0] out_data,10 output wire [7:0] out_data, 11 11 output wire out_flag 12 12 ); 13 13 14 14 reg out_flag_reg [2:0], out_flag_next [2:0]; 15 reg [ 6:0] out_data_reg [2:0], out_data_next [2:0];15 reg [7:0] out_data_reg [2:0], out_data_next [2:0]; 16 16 reg [5:0] inp_flag_reg, inp_flag_next; 17 17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0]; 18 reg [15:0] int_pipe_reg [ 19:0], int_pipe_next [19:0];19 reg [ 1:0] int_data_reg [3:0], int_data_next [3:0];18 reg [15:0] int_pipe_reg [23:0], int_pipe_next [23:0]; 19 reg [2:0] int_data_reg [3:0], int_data_next [3:0]; 20 20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0]; 21 21 22 22 wire [width-1:0] inp_data_wire [5:0]; 23 23 wire [3:0] int_pipe_wire [5:0]; 24 wire [1 5:0] int_comp_wire;24 wire [19:0] int_comp_wire; 25 25 26 26 integer i; … … 43 43 for (j = 0; j < 4; j = j + 1) 44 44 begin : CLASSIFIER_COMPARTORS 45 assign int_comp_wire[j*3+0+4] = (inp_data_reg[j+2] > cfg_data[(j*3+0+6)*width+width-1:(j*3+0+6)*width]); 46 assign int_comp_wire[j*3+1+4] = (inp_data_reg[j+2] > cfg_data[(j*3+1+6)*width+width-1:(j*3+1+6)*width]); 47 assign int_comp_wire[j*3+2+4] = (inp_data_reg[j+2] > cfg_data[(j*3+2+6)*width+width-1:(j*3+2+6)*width]); 45 assign int_comp_wire[j*4+0+4] = (inp_data_reg[j+2] > cfg_data[(j*4+0+6)*width+width-1:(j*4+0+6)*width]); 46 assign int_comp_wire[j*4+1+4] = (inp_data_reg[j+2] > cfg_data[(j*4+1+6)*width+width-1:(j*4+1+6)*width]); 47 assign int_comp_wire[j*4+2+4] = (inp_data_reg[j+2] > cfg_data[(j*4+2+6)*width+width-1:(j*4+2+6)*width]); 48 assign int_comp_wire[j*4+3+4] = (inp_data_reg[j+2] > cfg_data[(j*4+3+6)*width+width-1:(j*4+3+6)*width]); 48 49 end 49 50 endgenerate … … 54 55 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]); 55 56 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]); 56 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j* 3+0+8]);57 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j* 3+1+8]);58 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j* 3+2+8]);59 assign int_pipe_wire[j+2][3] = 1'b0;57 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*4+0+8]); 58 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*4+1+8]); 59 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*4+2+8]); 60 assign int_pipe_wire[j+2][3] = (|int_pipe_reg[j*4+3+8]); 60 61 end 61 62 endgenerate … … 68 69 for (i = 0; i < 3; i = i + 1) 69 70 begin 70 out_data_reg[i] <= {( 6){1'b0}};71 out_data_reg[i] <= {(7){1'b0}}; 71 72 out_flag_reg[i] <= 1'b0; 72 73 end … … 75 76 inp_data_reg[i] <= {(width){1'b0}}; 76 77 end 77 for (i = 0; i < 2 0; i = i + 1)78 for (i = 0; i < 24; i = i + 1) 78 79 begin 79 80 int_pipe_reg[i] <= {(16){1'b0}}; … … 81 82 for (i = 0; i < 4; i = i + 1) 82 83 begin 83 int_data_reg[i] <= {( 2){1'b0}};84 int_data_reg[i] <= {(3){1'b0}}; 84 85 end 85 86 for (i = 0; i < 2; i = i + 1) … … 100 101 inp_data_reg[i] <= inp_data_next[i]; 101 102 end 102 for (i = 0; i < 2 0; i = i + 1)103 for (i = 0; i < 24; i = i + 1) 103 104 begin 104 105 int_pipe_reg[i] <= int_pipe_next[i]; … … 127 128 inp_data_next[i] = inp_data_reg[i]; 128 129 end 129 for (i = 0; i < 2 0; i = i + 1)130 for (i = 0; i < 24; i = i + 1) 130 131 begin 131 132 int_pipe_next[i] = int_pipe_reg[i]; … … 152 153 for (i = 0; i < 3; i = i + 1) 153 154 begin 154 out_data_next[i] = {( 6){1'b0}};155 out_data_next[i] = {(7){1'b0}}; 155 156 out_flag_next[i] = 1'b0; 156 157 end 157 for (i = 0; i < 2 0; i = i + 1)158 for (i = 0; i < 24; i = i + 1) 158 159 begin 159 160 int_pipe_next[i] = {(16){1'b0}}; … … 164 165 else 165 166 begin 166 out_data_next[0] = {( 6){1'b0}};167 out_data_next[0] = {(7){1'b0}}; 167 168 out_data_next[1] = out_data_reg[0]; 168 169 out_data_next[2] = out_data_reg[1]; … … 172 173 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]); 173 174 175 for (i = 0; i < 5; i = i + 1) 176 begin 177 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 178 end 179 for (i = 4; i < 8; i = i + 1) 180 begin 181 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]}; 182 end 183 for (i = 8; i < 24; i = i + 1) 184 begin 185 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]}; 186 end 187 174 188 for (i = 0; i < 4; i = i + 1) 175 189 begin 176 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]}; 177 end 178 for (i = 4; i < 8; i = i + 1) 179 begin 180 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]}; 181 end 182 for (i = 8; i < 20; i = i + 1) 183 begin 184 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]}; 185 end 186 187 for (i = 0; i < 4; i = i + 1) 188 begin 189 case (int_pipe_wire[i+2][2:0]) 190 3'b000: int_data_next[i] = 2'b00; 191 3'b001: int_data_next[i] = 2'b01; 192 3'b011: int_data_next[i] = 2'b10; 193 3'b111: int_data_next[i] = 2'b11; 194 default: int_data_next[i] = 2'd0; 190 case (int_pipe_wire[i+2][3:0]) 191 4'b0000: int_data_next[i] = 3'b000; 192 4'b0001: int_data_next[i] = 3'b001; 193 4'b0011: int_data_next[i] = 3'b010; 194 4'b0111: int_data_next[i] = 3'b011; 195 4'b1111: int_data_next[i] = 3'b100; 196 default: int_data_next[i] = 3'b000; 195 197 endcase 196 198 end … … 200 202 201 203 case (int_temp_reg[0][4:0]) 202 5'b00011: out_data_next[0][ 3:0] = {2'b00, int_data_next[0]};203 5'b00111: out_data_next[0][ 3:0] = {2'b01, int_data_next[1]};204 5'b01111: out_data_next[0][ 3:0] = {2'b10, int_data_next[2]};205 5'b11111: out_data_next[0][ 3:0] = {2'b11, int_data_next[3]};204 5'b00011: out_data_next[0][4:0] = int_data_next[0]; 205 5'b00111: out_data_next[0][4:0] = int_data_next[1] + 4'd5; 206 5'b01111: out_data_next[0][4:0] = int_data_next[2] + 4'd10; 207 5'b11111: out_data_next[0][4:0] = int_data_next[3] + 4'd15; 206 208 default: out_flag_next[0] = 1'b0; 207 209 endcase … … 209 211 case (int_temp_reg[1][3:0]) 210 212 // S1_F, electron 211 4'b0001: out_data_next[0][ 6:4] = 3'b100;213 4'b0001: out_data_next[0][7:5] = 3'b100; 212 214 213 215 // S1_F, proton 214 4'b0010: out_data_next[0][ 6:4] = 3'b101;216 4'b0010: out_data_next[0][7:5] = 3'b101; 215 217 216 218 // S1_S, electron 217 4'b0100: out_data_next[0][ 6:4] = 3'b110;219 4'b0100: out_data_next[0][7:5] = 3'b110; 218 220 219 221 // S1_S, proton 220 4'b1000: out_data_next[0][ 6:4] = 3'b111;222 4'b1000: out_data_next[0][7:5] = 3'b111; 221 223 222 224 default: out_flag_next[0] = 1'b0; -
trunk/3DEES/histogram32.v
r180 r186 4 4 5 5 input wire hst_good, 6 input wire [ 5:0]hst_data,6 input wire [6:0] hst_data, 7 7 8 8 input wire bus_ssel, bus_wren, … … 17 17 reg [3:0] int_case_reg, int_case_next; 18 18 reg int_wren_reg, int_wren_next; 19 reg [ 5:0] int_addr_reg, int_addr_next;19 reg [6:0] int_addr_reg, int_addr_next; 20 20 reg [31:0] int_data_reg, int_data_next; 21 21 … … 38 38 .intended_device_family("Cyclone III"), 39 39 .lpm_type("altsyncram"), 40 .numwords_a( 64),41 .numwords_b(1 28),40 .numwords_a(80), 41 .numwords_b(160), 42 42 .operation_mode("BIDIR_DUAL_PORT"), 43 43 .outdata_aclr_a("NONE"), … … 49 49 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"), 50 50 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"), 51 .widthad_a( 6),52 .widthad_b( 7),51 .widthad_a(7), 52 .widthad_b(8), 53 53 .width_a(32), 54 54 .width_b(16), … … 86 86 begin 87 87 int_wren_reg <= 1'b1; 88 int_addr_reg <= 6'd0;88 int_addr_reg <= 7'd0; 89 89 int_data_reg <= 32'd0; 90 90 int_case_reg <= 4'b0; … … 139 139 begin 140 140 // write zeros 141 int_addr_next = int_addr_reg + 6'd1;141 int_addr_next = int_addr_reg + 7'd1; 142 142 if (&int_addr_reg) 143 143 begin … … 187 187 begin 188 188 int_wren_next = 1'b0; 189 int_addr_next = 6'd0;189 int_addr_next = 7'd0; 190 190 int_data_next = 32'd0; 191 191 int_case_next = 4'd0;
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