- Timestamp:
- Sep 9, 2011, 11:28:15 AM (13 years ago)
- File:
-
- 1 edited
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sandbox/MultiChannelUSB/oscilloscope.v
r103 r157 130 130 if (bus_ssel) 131 131 begin 132 bus_miso_next = {ram_data[17:10], ram_data[8:1]};132 bus_miso_next = ram_data[15:0]; 133 133 ram_wren_next[0] = bus_wren; 134 134 if (bus_wren) … … 183 183 ram_addr_next = ram_addr_reg + 20'd1; 184 184 ram_wren_next[0] = 1'b1; 185 ram_data_next[0] = { osc_data[15:8], 1'b0, osc_data[7:0], 1'b0};185 ram_data_next[0] = {2'd0, osc_data[15:0]}; 186 186 187 187 int_case_next = 3'd3; … … 211 211 ram_addr_next = ram_addr_reg + 20'd1; 212 212 ram_wren_next[0] = 1'b1; 213 ram_data_next[0] = { osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};213 ram_data_next[0] = {2'd0, osc_data_reg[31:16]}; 214 214 int_case_next = 3'd4; 215 215 end … … 219 219 ram_addr_next = ram_addr_reg + 20'd1; 220 220 ram_wren_next[0] = 1'b1; 221 ram_data_next[0] = { osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};221 ram_data_next[0] = {2'd0, osc_data_reg[47:32]}; 222 222 int_case_next = 3'd5; 223 223 end … … 227 227 ram_addr_next = ram_addr_reg + 20'd1; 228 228 ram_wren_next[0] = 1'b1; 229 ram_data_next[0] = { osc_data_reg[63:56], 1'b0, osc_data_reg[55:48], 1'b0};229 ram_data_next[0] = {2'd0, osc_data_reg[63:48]}; 230 230 if (|int_cntr_reg[0]) 231 231 begin
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