- Timestamp:
- Jun 27, 2011, 12:59:27 AM (13 years ago)
- File:
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- 1 edited
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sandbox/MultiChannelUSB/filter.v (modified) (5 diffs)
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sandbox/MultiChannelUSB/filter.v
r131 r156 10 10 ); 11 11 12 localparam widthr = width + 13; 13 12 localparam widthr = width + 7; 14 13 /* 15 4-bit LFSR with additional bits to keep track of previous values14 5-bit LFSR with additional bits to keep track of previous values 16 15 */ 17 reg [ 15:0] int_lfsr_reg, int_lfsr_next;16 reg [23:0] int_lfsr_reg, int_lfsr_next; 18 17 19 18 reg int_wren_reg, int_wren_next; 20 reg [1:0] int_chan_reg, int_chan_next; 21 reg [2:0] int_case_reg, int_case_next; 22 reg [7:0] int_addr_reg, int_addr_next; 23 24 wire [9:0] int_addr_wire; 25 26 reg [size*widthr-1:0] acc_data_reg [3:0], acc_data_next [3:0]; 27 reg [size*widthr-1:0] int_data_reg [8:0], int_data_next [8:0]; 28 29 wire [size*widthr-1:0] acc_data_wire [3:0], del_data_wire [1:0]; 19 reg int_flag_reg, int_flag_next; 20 reg int_chan_reg, int_chan_next; 21 reg [1:0] int_case_reg, int_case_next; 22 reg [5:0] int_addr_reg, int_addr_next; 23 24 wire [5:0] int_addr_wire; 25 26 reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0]; 27 reg [size*widthr-1:0] int_data_reg [2:0], int_data_next [2:0]; 28 29 wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire; 30 30 31 31 integer i; … … 37 37 assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]}; 38 38 39 // -2*del_data_1 + del_data_2 + inp_data + result40 41 39 assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] = 42 40 acc_data_reg[0][j*widthr+widthr-1:j*widthr] 43 + del_data_wire[1][j*widthr+widthr-1:j*widthr] 44 - {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0}; 45 46 assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] = 47 acc_data_reg[1][j*widthr+widthr-1:j*widthr] 48 + acc_data_reg[2][j*widthr+widthr-1:j*widthr]; 49 50 assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] = 51 acc_data_reg[2][j*widthr+widthr-1:j*widthr] 52 + acc_data_reg[3][j*widthr+widthr-1:j*widthr]; 41 - del_data_wire[j*widthr+widthr-1:j*widthr] 42 + acc_data_reg[1][j*widthr+widthr-1:j*widthr]; 53 43 54 44 end 55 45 endgenerate 56 46 57 cic_pipeline #( 58 .width(size*widthr)) cic_pipeline_unit ( 59 .clock(clock), 60 .data(acc_data_reg[0]), 61 .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}), 62 .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}), 63 .wraddress(int_addr_reg), 64 .wren(int_wren_reg), 65 .qa(del_data_wire[0]), 66 .qb(del_data_wire[1])); 47 altsyncram #( 48 .address_aclr_b("NONE"), 49 .address_reg_b("CLOCK0"), 50 .clock_enable_input_a("BYPASS"), 51 .clock_enable_input_b("BYPASS"), 52 .clock_enable_output_b("BYPASS"), 53 .intended_device_family("Cyclone III"), 54 .lpm_type("altsyncram"), 55 .numwords_a(64), 56 .numwords_b(64), 57 .operation_mode("DUAL_PORT"), 58 .outdata_aclr_b("NONE"), 59 .outdata_reg_b("CLOCK0"), 60 .power_up_uninitialized("FALSE"), 61 .read_during_write_mode_mixed_ports("DONT_CARE"), 62 .widthad_a(6), 63 .widthad_b(6), 64 .width_a(size*widthr), 65 .width_b(size*widthr), 66 .width_byteena_a(1)) ram_unit_1 ( 67 .wren_a(int_wren_reg), 68 .clock0(clock), 69 .address_a(int_addr_reg), 70 .address_b(int_addr_wire), 71 .data_a(acc_data_reg[0]), 72 .q_b(del_data_wire), 73 .aclr0(1'b0), 74 .aclr1(1'b0), 75 .addressstall_a(1'b0), 76 .addressstall_b(1'b0), 77 .byteena_a(1'b1), 78 .byteena_b(1'b1), 79 .clock1(1'b1), 80 .clocken0(1'b1), 81 .clocken1(1'b1), 82 .clocken2(1'b1), 83 .clocken3(1'b1), 84 .data_b({(size*widthr){1'b1}}), 85 .eccstatus(), 86 .q_a(), 87 .rden_a(1'b1), 88 .rden_b(1'b1), 89 .wren_b(1'b0)); 67 90 68 91 lpm_mux #( 69 .lpm_size( 3),92 .lpm_size(2), 70 93 .lpm_type("LPM_MUX"), 71 .lpm_width( 10),72 .lpm_widths( 2)) mux_unit_1 (94 .lpm_width(6), 95 .lpm_widths(1)) mux_unit_1 ( 73 96 .sel(int_chan_next), 74 97 .data({ 75 2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5], 76 2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4], 77 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}), 78 .result(int_addr_wire)); 98 1'b1, int_lfsr_reg[16+4:16], 99 1'b0, int_lfsr_reg[4+4:4]}), 100 .result(int_addr_wire)); 79 101 80 102 always @(posedge clock) … … 83 105 begin 84 106 int_wren_reg <= 1'b1; 85 int_chan_reg <= 2'd0; 86 int_case_reg <= 3'd0; 87 int_addr_reg <= 8'd0; 88 for(i = 0; i <= 3; i = i + 1) 107 int_flag_reg <= 1'b0; 108 int_chan_reg <= 1'b0; 109 int_case_reg <= 2'd0; 110 int_addr_reg <= 6'd0; 111 for(i = 0; i <= 1; i = i + 1) 89 112 begin 90 113 acc_data_reg[i] <= {(size*widthr){1'b0}}; 91 114 end 92 for(i = 0; i <= 8; i = i + 1)115 for(i = 0; i <= 2; i = i + 1) 93 116 begin 94 117 int_data_reg[i] <= {(size*widthr){1'b0}}; 95 118 end 96 int_lfsr_reg <= 16'd0;119 int_lfsr_reg <= 24'd0; 97 120 end 98 121 else 99 122 begin 100 123 int_wren_reg <= int_wren_next; 124 int_flag_reg <= int_flag_next; 101 125 int_chan_reg <= int_chan_next; 102 126 int_case_reg <= int_case_next; 103 127 int_addr_reg <= int_addr_next; 104 for(i = 0; i <= 3; i = i + 1)128 for(i = 0; i <= 1; i = i + 1) 105 129 begin 106 130 acc_data_reg[i] <= acc_data_next[i]; 107 131 end 108 for(i = 0; i <= 8; i = i + 1)132 for(i = 0; i <= 2; i = i + 1) 109 133 begin 110 134 int_data_reg[i] <= int_data_next[i]; … … 117 141 begin 118 142 int_wren_next = int_wren_reg; 143 int_flag_next = int_flag_reg; 119 144 int_chan_next = int_chan_reg; 120 145 int_case_next = int_case_reg; 121 146 int_addr_next = int_addr_reg; 122 for(i = 0; i <= 3; i = i + 1)147 for(i = 0; i <= 1; i = i + 1) 123 148 begin 124 149 acc_data_next[i] = acc_data_reg[i]; 125 150 end 126 for(i = 0; i <= 8; i = i + 1)151 for(i = 0; i <= 2; i = i + 1) 127 152 begin 128 153 int_data_next[i] = int_data_reg[i]; … … 135 160 // write zeros 136 161 int_wren_next = 1'b1; 137 int_addr_next = 8'd0;138 for(i = 0; i <= 3; i = i + 1)162 int_addr_next = 6'd0; 163 for(i = 0; i <= 1; i = i + 1) 139 164 begin 140 165 acc_data_next[i] = {(size*widthr){1'b0}}; 141 166 end 142 for(i = 0; i <= 8; i = i + 1)167 for(i = 0; i <= 2; i = i + 1) 143 168 begin 144 169 int_data_next[i] = {(size*widthr){1'b0}}; 145 170 end 146 int_case_next = 3'd1;171 int_case_next = 2'd1; 147 172 end 148 173 1: 149 174 begin 150 175 // write zeros 151 int_addr_next = int_addr_reg + 8'd1;176 int_addr_next = int_addr_reg + 6'd1; 152 177 if (&int_addr_reg) 153 178 begin 154 179 int_wren_next = 1'b0; 155 int_chan_next = 2'd0; 156 int_lfsr_next = 16'h7650; 157 int_case_next = 3'd2; 180 int_flag_next = 1'b0; 181 int_chan_next = 1'b0; 182 int_lfsr_next = 24'h0722BD; 183 int_case_next = 'd2; 158 184 end 159 185 end 160 186 2: // frame 161 187 begin 188 int_flag_next = 1'b0; 162 189 if (frame) 163 190 begin 164 191 int_wren_next = 1'b1; 165 192 166 int_addr_next = { 4'd0, int_lfsr_reg[3:0]};193 int_addr_next = {1'b0, int_lfsr_reg[4:0]}; 167 194 168 195 // set read addr for 2nd pipeline 169 int_chan_next = 2'd1;196 int_chan_next = 1'b1; 170 197 171 198 // prepare registers for 1st sum 172 199 acc_data_next[0] = acc_data_wire[0]; 173 200 acc_data_next[1] = int_data_reg[0]; 174 acc_data_next[2] = int_data_reg[1];175 acc_data_next[3] = int_data_reg[2];176 201 177 int_case_next = 3'd3; 178 end 179 180 end 181 3: // 1st sum 202 int_lfsr_next = {int_lfsr_reg[22:0], int_lfsr_reg[2] ~^ int_lfsr_reg[4]}; 203 204 int_case_next = 'd3; 205 end 206 if (int_flag_reg) // register 2nd sum 207 begin 208 // register 2nd sum 209 int_data_next[1] = acc_data_wire[1]; 210 end 211 end 212 3: // 2nd sum 182 213 begin 183 int_addr_next = {4'd1, int_lfsr_reg[3:0]}; 184 185 // set read addr for 3rd pipeline 186 int_chan_next = 2'd2; 214 int_flag_next = 1'b1; 215 216 int_addr_next = {1'b1, int_lfsr_reg[5:1]}; 217 218 // set read addr for 1st pipeline 219 int_chan_next = 1'b0; 187 220 188 221 // prepare registers for 2nd sum 189 acc_data_next[0] = int_data_reg[2]; 190 acc_data_next[1] = int_data_reg[3]; 191 acc_data_next[2] = int_data_reg[4]; 192 acc_data_next[3] = int_data_reg[5]; 222 acc_data_next[0] = int_data_reg[0]; 223 acc_data_next[1] = int_data_reg[1]; 193 224 194 225 // register 1st sum 195 226 int_data_next[0] = acc_data_wire[1]; 196 int_data_next[1] = acc_data_wire[2];197 int_data_next[2] = acc_data_wire[3];198 199 int_case_next = 3'd4;200 end201 4: // 2nd sum202 begin203 int_addr_next = {4'd2, int_lfsr_reg[3:0]};204 205 // prepare registers for 3rd sum206 acc_data_next[0] = int_data_reg[5];207 acc_data_next[1] = int_data_reg[6];208 acc_data_next[2] = int_data_reg[7];209 acc_data_next[3] = int_data_reg[8];210 211 // register 2nd sum212 int_data_next[3] = acc_data_wire[1];213 int_data_next[4] = acc_data_wire[2];214 int_data_next[5] = acc_data_wire[3];215 227 216 int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]}; 217 218 int_case_next = 3'd5; 219 end 220 5: // 3rd sum 221 begin 222 int_wren_next = 1'b0; 223 224 // set read addr for 1st pipeline 225 int_chan_next = 2'd0; 226 227 // register 3rd sum 228 int_data_next[6] = acc_data_wire[1]; 229 int_data_next[7] = acc_data_wire[2]; 230 int_data_next[8] = acc_data_wire[3]; 231 232 int_case_next = 3'd2; 228 // register 2nd output 229 int_data_next[2] = int_data_reg[1]; 230 231 int_case_next = 2'd2; 233 232 end 234 233 default: 235 234 begin 236 int_case_next = 3'd0;235 int_case_next = 2'd0; 237 236 end 238 237 endcase 239 238 end 240 239 241 assign out_data = int_data_reg[ 8];240 assign out_data = int_data_reg[2]; 242 241 243 242 endmodule
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