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1 | module Paella
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2 | (
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3 | input wire CLK_50MHz,
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4 | output wire LED,
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5 |
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6 | inout wire [3:0] TRG,
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7 | inout wire [6:0] CON_A,
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8 | inout wire [16:0] CON_B,
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9 | inout wire [11:0] CON_C,
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10 | input wire [1:0] CON_BCLK,
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11 | input wire [1:0] CON_CCLK,
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12 |
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13 | input wire ADC_DCO,
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14 | input wire ADC_FCO,
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15 | input wire ADC_DB,
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16 | input wire ADC_DC,
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17 | input wire ADC_DD,
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18 |
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19 | inout wire USB_SLDR,
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20 | inout wire USB_SLWR,
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21 | inout wire USB_IFCLK,
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22 | inout wire USB_FLAGA,
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23 | inout wire USB_FLAGB,
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24 | input wire USB_FLAGC,
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25 | inout wire [7:0] USB_PA,
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26 | inout wire [7:0] USB_PB,
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27 |
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28 | inout wire RAM_CLK,
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29 | inout wire RAM_CE1,
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30 | inout wire RAM_WE,
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31 | output wire [19:0] RAM_ADDR,
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32 | inout wire RAM_DQAP,
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33 | inout wire [7:0] RAM_DQA,
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34 | inout wire RAM_DQBP,
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35 | inout wire [7:0] RAM_DQB
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36 | );
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37 |
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38 | reg [31:0] counter;
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39 |
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40 | assign LED = counter[25];
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41 |
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42 | always @ (posedge CLK_50MHz)
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43 | begin
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44 | counter <= counter + 32'd1;
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45 | end
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46 |
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47 | endmodule
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