source: trunk/MultiChannelUSB/oscilloscope.v@ 91

Last change on this file since 91 was 91, checked in by demin, 15 years ago

fix communication with external SRAM
File size: 5.1 KB
Line 
1module oscilloscope
2 (
3 input wire clock, frame, reset,
4
5 input wire [16:0] cfg_data,
6
7 input wire trg_flag,
8
9 input wire [47:0] osc_data,
10
11 output wire ram_wren,
12 output wire [19:0] ram_addr,
13 inout wire [17:0] ram_data,
14
15 input wire bus_ssel, bus_wren,
16 input wire [19:0] bus_addr,
17 input wire [15:0] bus_mosi,
18
19 output wire [15:0] bus_miso,
20 output wire bus_busy
21 );
22
23
24 reg [47:0] osc_data_reg, osc_data_next;
25
26 reg [2:0] int_case_reg, int_case_next;
27
28 reg int_trig_reg, int_trig_next;
29 reg [19:0] int_trig_addr_reg, int_trig_addr_next;
30
31 reg [19:0] int_cntr_reg [1:0];
32 reg [19:0] int_cntr_next [1:0];
33
34 reg [15:0] bus_mosi_reg [2:0];
35 reg [15:0] bus_mosi_next [2:0];
36
37 reg [15:0] bus_miso_reg, bus_miso_next;
38 reg bus_busy_reg, bus_busy_next;
39
40 reg ram_wren_reg [2:0];
41 reg ram_wren_next [2:0];
42
43 reg [17:0] ram_data_reg, ram_data_next;
44 reg [19:0] ram_addr_reg, ram_addr_next;
45
46 wire [17:0] ram_wren_wire;
47
48 assign ram_wren = ~ram_wren_reg[0];
49 assign ram_addr = ram_addr_reg;
50
51 integer i;
52 genvar j;
53
54 generate
55 for (j = 0; j < 18; j = j + 1)
56 begin : SRAM_WREN
57 assign ram_wren_wire[j] = ram_wren_reg[2];
58 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[j] : 1'bz;
59 end
60 endgenerate
61
62 always @(posedge clock)
63 begin
64 if (reset)
65 begin
66 osc_data_reg <= 48'd0;
67 ram_data_reg <= 18'd0;
68 ram_addr_reg <= 20'd0;
69 bus_miso_reg <= 16'd0;
70 bus_busy_reg <= 1'b0;
71 int_case_reg <= 5'd0;
72 int_cntr_reg[0] <= 20'd0;
73 int_cntr_reg[1] <= 20'd0;
74 int_trig_reg <= 1'b0;
75 int_trig_addr_reg <= 20'd0;
76
77 for(i = 0; i <= 2; i = i + 1)
78 begin
79 ram_wren_reg[i] <= 1'b0;
80 bus_mosi_reg[i] <= 16'd0;
81 end
82 end
83 else
84 begin
85 osc_data_reg <= osc_data_next;
86 ram_data_reg <= ram_data_next;
87 ram_addr_reg <= ram_addr_next;
88 bus_miso_reg <= bus_miso_next;
89 bus_busy_reg <= bus_busy_next;
90 int_case_reg <= int_case_next;
91 int_cntr_reg[0] <= int_cntr_next[0];
92 int_cntr_reg[1] <= int_cntr_next[1];
93 int_trig_reg <= int_trig_next;
94 int_trig_addr_reg <= int_trig_addr_next;
95
96 for(i = 0; i <= 2; i = i + 1)
97 begin
98 ram_wren_reg[i] <= ram_wren_next[i];
99 bus_mosi_reg[i] <= bus_mosi_next[i];
100 end
101 end
102 end
103
104 always @*
105 begin
106
107 osc_data_next = osc_data_reg;
108 ram_data_next = ram_data_reg;
109 ram_addr_next = ram_addr_reg;
110 bus_miso_next = bus_miso_reg;
111 bus_busy_next = bus_busy_reg;
112 int_case_next = int_case_reg;
113 int_cntr_next[0] = int_cntr_reg[0];
114 int_cntr_next[1] = int_cntr_reg[1];
115 int_trig_next = int_trig_reg;
116 int_trig_addr_next = int_trig_addr_reg;
117
118 for(i = 0; i < 2; i = i + 1)
119 begin
120 ram_wren_next[i+1] = ram_wren_reg[i];
121 bus_mosi_next[i+1] = bus_mosi_reg[i];
122 end
123 ram_wren_next[0] = 1'b0;
124 bus_mosi_next[0] = 16'd0;
125
126 case (int_case_reg)
127 0:
128 begin
129 ram_data_next = 18'd0;
130 ram_addr_next = 20'd0;
131 bus_busy_next = 1'b0;
132 int_cntr_next[0] = 20'd0;
133 int_cntr_next[1] = 20'd0;
134 int_trig_next = 1'b0;
135
136 ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};
137
138 if (bus_ssel)
139 begin
140 bus_miso_next = {ram_data[17:10], ram_data[8:1]};
141 ram_wren_next[0] = bus_wren;
142 if (bus_wren)
143 begin
144 ram_addr_next = bus_addr;
145 bus_mosi_next[0] = bus_mosi;
146 end
147 else
148 begin
149// ram_addr_next = int_trig_addr_reg + bus_addr;
150 ram_addr_next = bus_addr;
151 end
152 end
153 else if (cfg_data[16])
154 begin
155 // start recording
156 ram_wren_next[0] = 1'b1;
157 bus_busy_next = 1'b1;
158 int_case_next = 3'd1;
159 int_trig_addr_next = 20'd0;
160 int_cntr_next[0] = {cfg_data[7:0], 10'd0};
161 int_cntr_next[1] = {cfg_data[15:8], 10'd0};
162 end
163
164 end
165
166 // sample recording
167 1:
168 begin
169 ram_wren_next[0] = 1'b1;
170 if (frame)
171 begin
172 osc_data_next = osc_data;
173 ram_addr_next = ram_addr_reg + 20'd1;
174 int_case_next = 3'd2;
175
176 if ((~int_trig_reg) & (trg_flag) & (int_cntr_reg[1] == 0))
177 begin
178 int_trig_next = 1'b1;
179 int_trig_addr_next = ram_addr_reg;
180 end
181
182 if ((int_trig_reg) & (|int_cntr_reg[0]))
183 begin
184 int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
185 end
186
187 if ((|int_cntr_reg[1]))
188 begin
189 int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
190 end
191 end
192 end
193
194 2:
195 begin
196 ram_wren_next[0] = 1'b1;
197 ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0};
198 ram_addr_next = ram_addr_reg + 20'd1;
199 int_case_next = 3'd3;
200 end
201
202 3:
203 begin
204 ram_wren_next[0] = 1'b1;
205 ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
206 ram_addr_next = ram_addr_reg + 20'd1;
207 int_case_next = 3'd4;
208 end
209
210 4:
211 begin
212 ram_wren_next[0] = 1'b1;
213 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
214 int_case_next = 3'd1;
215 if (int_cntr_reg[0] == 0)
216 begin
217 ram_wren_next[0] = 1'b0;
218 ram_addr_next = 20'd0;
219 int_case_next = 3'd0;
220 end
221 end
222
223 endcase
224 end
225
226 assign bus_miso = bus_miso_reg;
227 assign bus_busy = bus_busy_reg;
228
229endmodule
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