[27] | 1 | module histogram
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[72] | 2 | #(
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| 3 | parameter W = 32 // bin resolution
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| 4 | )
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[27] | 5 | (
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| 6 | input wire clk, reset,
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| 7 | input wire data_ready,
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| 8 | input wire [11:0] data, address,
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[72] | 9 | output wire [W-1:0] q
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[27] | 10 | );
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| 11 |
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| 12 | // signal declaration
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| 13 | reg [3:0] state_reg, state_next;
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| 14 | reg wren_reg, wren_next;
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| 15 | reg [11:0] addr_reg, addr_next;
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[72] | 16 | reg [W-1:0] data_reg, data_next;
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[27] | 17 |
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[72] | 18 | wire [W-1:0] q_a_wire, q_b_wire;
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[27] | 19 |
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[47] | 20 | altsyncram #(
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| 21 | .address_reg_b("CLOCK0"),
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| 22 | .clock_enable_input_a("BYPASS"),
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| 23 | .clock_enable_input_b("BYPASS"),
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| 24 | .clock_enable_output_a("BYPASS"),
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| 25 | .clock_enable_output_b("BYPASS"),
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| 26 | .indata_reg_b("CLOCK0"),
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| 27 | .intended_device_family("Cyclone III"),
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| 28 | .lpm_type("altsyncram"),
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| 29 | .numwords_a(4096),
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| 30 | .numwords_b(4096),
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| 31 | .operation_mode("BIDIR_DUAL_PORT"),
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| 32 | .outdata_aclr_a("NONE"),
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| 33 | .outdata_aclr_b("NONE"),
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[84] | 34 | .outdata_reg_a("CLOCK0"),
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| 35 | .outdata_reg_b("CLOCK0"),
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[47] | 36 | .power_up_uninitialized("FALSE"),
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| 37 | .read_during_write_mode_mixed_ports("OLD_DATA"),
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| 38 | .widthad_a(12),
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| 39 | .widthad_b(12),
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[72] | 40 | .width_a(W),
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| 41 | .width_b(W),
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[47] | 42 | .width_byteena_a(1),
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| 43 | .width_byteena_b(1),
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[51] | 44 | .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
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| 45 | .wren_a(wren_reg),
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[52] | 46 | .clock0(clk),
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[51] | 47 | .wren_b(1'b0),
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[84] | 48 | .address_a(addr_reg),
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[51] | 49 | .address_b(address),
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[84] | 50 | .data_a(data_reg),
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[51] | 51 | .data_b(),
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| 52 | .q_a(q_a_wire),
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| 53 | .q_b(q_b_wire),
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| 54 | .aclr0(1'b0),
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| 55 | .aclr1(1'b0),
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| 56 | .addressstall_a(1'b0),
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| 57 | .addressstall_b(1'b0),
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| 58 | .byteena_a(1'b1),
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| 59 | .byteena_b(1'b1),
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| 60 | .clock1(1'b1),
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| 61 | .clocken0(1'b1),
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| 62 | .clocken1(1'b1),
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| 63 | .clocken2(1'b1),
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| 64 | .clocken3(1'b1),
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| 65 | .eccstatus(),
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| 66 | .rden_a(1'b1),
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| 67 | .rden_b(1'b1));
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[27] | 68 |
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| 69 | // body
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| 70 | always @(posedge clk)
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| 71 | begin
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| 72 | if (reset)
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| 73 | begin
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[51] | 74 | wren_reg <= 1'b1;
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| 75 | addr_reg <= 12'd0;
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[70] | 76 | data_reg <= 32'd0;
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[27] | 77 | state_reg <= 4'b1;
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| 78 | end
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| 79 | else
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| 80 | begin
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| 81 | wren_reg <= wren_next;
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| 82 | addr_reg <= addr_next;
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| 83 | data_reg <= data_next;
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[51] | 84 | state_reg <= state_next;
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[27] | 85 | end
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| 86 | end
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| 87 |
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| 88 | always @*
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| 89 | begin
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| 90 | wren_next = wren_reg;
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| 91 | addr_next = addr_reg;
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| 92 | data_next = data_reg;
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[51] | 93 | state_next = state_reg;
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[27] | 94 | case (state_reg)
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[51] | 95 | 0:
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[27] | 96 | begin
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[51] | 97 | // nothing to do
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| 98 | wren_next = 1'b0;
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| 99 | addr_next = 12'd0;
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[70] | 100 | data_next = 32'd0;
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[51] | 101 | state_next = 4'd0;
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[27] | 102 | end
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[51] | 103 |
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| 104 | 1:
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[27] | 105 | begin
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| 106 | // write zeros
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| 107 | if (&addr_reg)
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| 108 | begin
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[51] | 109 | wren_next = 1'b0;
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| 110 | state_next = 4'd2;
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[27] | 111 | end
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| 112 | else
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| 113 | begin
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| 114 | addr_next = addr_reg + 12'd1;
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| 115 | end
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[51] | 116 | end
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| 117 |
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| 118 | 2:
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[27] | 119 | begin
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[84] | 120 | wren_next = 1'b0;
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[51] | 121 | if (data_ready)
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[27] | 122 | begin
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[84] | 123 | addr_next = data;
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| 124 | state_next = 4'd3;
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[27] | 125 | end
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| 126 | end
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| 127 |
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[51] | 128 | 3:
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[27] | 129 | begin
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[84] | 130 | state_next = 4'd4;
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[27] | 131 | end
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| 132 |
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[84] | 133 | 4:
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| 134 | begin
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[88] | 135 | state_next = 5'd4;
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| 136 | end
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| 137 |
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| 138 | 5:
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| 139 | begin
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[84] | 140 | if (&q_a_wire)
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| 141 | begin
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| 142 | state_next = 4'd0;
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| 143 | end
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| 144 | else
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| 145 | begin
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| 146 | wren_next = 1'b1;
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| 147 | data_next = q_a_wire + 32'd1;
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| 148 | state_next = 4'd2;
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| 149 | end
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| 150 | end
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| 151 |
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[27] | 152 | default:
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| 153 | begin
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[51] | 154 | wren_next = 1'b0;
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| 155 | addr_next = 12'd0;
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[70] | 156 | data_next = 32'd0;
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[27] | 157 | state_next = 4'd0;
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| 158 | end
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| 159 | endcase
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| 160 | end
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| 161 |
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| 162 | // output logic
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[45] | 163 | assign q = q_b_wire;
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[27] | 164 | endmodule
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