Last change
on this file since 85 was 84, checked in by demin, 15 years ago |
improve timings in all components
|
File size:
1.4 KB
|
Rev | Line | |
---|
[27] | 1 | module adc_fifo
|
---|
| 2 | (
|
---|
| 3 | input wire adc_clk,
|
---|
| 4 | input wire [11:0] adc_data,
|
---|
| 5 |
|
---|
[58] | 6 | input wire clk,
|
---|
[72] | 7 | output wire data_ready,
|
---|
| 8 | output wire [11:0] data
|
---|
[27] | 9 | );
|
---|
| 10 |
|
---|
[72] | 11 | wire [11:0] int_q;
|
---|
| 12 | reg [11:0] int_data;
|
---|
[44] | 13 |
|
---|
[84] | 14 | reg [1:0] state;
|
---|
| 15 | reg int_rdreq, int_data_ready;
|
---|
[72] | 16 | wire int_wrfull, int_rdempty;
|
---|
[27] | 17 |
|
---|
[45] | 18 | dcfifo #(
|
---|
| 19 | .intended_device_family("Cyclone III"),
|
---|
| 20 | .lpm_numwords(16),
|
---|
| 21 | .lpm_showahead("ON"),
|
---|
| 22 | .lpm_type("dcfifo"),
|
---|
| 23 | .lpm_width(12),
|
---|
| 24 | .lpm_widthu(4),
|
---|
| 25 | .rdsync_delaypipe(4),
|
---|
| 26 | .wrsync_delaypipe(4),
|
---|
| 27 | .overflow_checking("ON"),
|
---|
| 28 | .underflow_checking("ON"),
|
---|
[84] | 29 | .use_eab("ON"),
|
---|
[72] | 30 | .write_aclr_synch("OFF")) fifo_unit (
|
---|
[58] | 31 | .aclr(1'b0),
|
---|
[72] | 32 | .data(adc_data),
|
---|
[58] | 33 | .rdclk(clk),
|
---|
[49] | 34 | .rdreq((~int_rdempty) & int_rdreq),
|
---|
[27] | 35 | .wrclk(adc_clk),
|
---|
[72] | 36 | .wrreq(~int_wrfull),
|
---|
| 37 | .q(int_q),
|
---|
[44] | 38 | .rdempty(int_rdempty),
|
---|
[72] | 39 | .wrfull(int_wrfull),
|
---|
[45] | 40 | .rdfull(),
|
---|
| 41 | .rdusedw(),
|
---|
| 42 | .wrempty(),
|
---|
| 43 | .wrusedw());
|
---|
[27] | 44 |
|
---|
[58] | 45 | always @(posedge clk)
|
---|
[44] | 46 | begin
|
---|
| 47 | case (state)
|
---|
[84] | 48 | 2'd0:
|
---|
[44] | 49 | begin
|
---|
[49] | 50 | int_rdreq <= 1'b1;
|
---|
[72] | 51 | int_data_ready <= 1'b0;
|
---|
[84] | 52 | state <= 2'd1;
|
---|
[49] | 53 | end
|
---|
| 54 |
|
---|
[84] | 55 | 2'd1:
|
---|
[49] | 56 | begin
|
---|
[44] | 57 | if (~int_rdempty)
|
---|
| 58 | begin
|
---|
[72] | 59 | int_data <= int_q;
|
---|
[49] | 60 | int_rdreq <= 1'b0;
|
---|
[72] | 61 | int_data_ready <= 1'b1;
|
---|
[84] | 62 | state <= 2'd0;
|
---|
[44] | 63 | end
|
---|
| 64 | end
|
---|
| 65 |
|
---|
[84] | 66 | 2'd2:
|
---|
[44] | 67 | begin
|
---|
[72] | 68 | int_data_ready <= 1'b0;
|
---|
[84] | 69 | state <= 2'd3;
|
---|
[44] | 70 | end
|
---|
[84] | 71 |
|
---|
| 72 | 2'd3:
|
---|
| 73 | begin
|
---|
| 74 | state <= 2'd0;
|
---|
| 75 | end
|
---|
| 76 |
|
---|
[44] | 77 | endcase
|
---|
| 78 | end
|
---|
| 79 |
|
---|
[72] | 80 | assign data_ready = int_data_ready;
|
---|
| 81 | assign data = int_data;
|
---|
[44] | 82 |
|
---|
[27] | 83 | endmodule
|
---|
Note:
See
TracBrowser
for help on using the repository browser.