source: trunk/MultiChannelUSB/Paella.v@ 36

Last change on this file since 36 was 35, checked in by demin, 16 years ago

first working version
File size: 8.1 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire ADC_DB,
16 input wire ADC_DC,
17 input wire ADC_DD,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46 assign RAM_CLK = 1'b0;
47 assign RAM_CE1 = 1'b0;
48 assign RAM_WE = 1'b0;
49 assign RAM_ADDR = 20'h00000;
50
51 // Turn inout ports to tri-state
52 assign TRG = 4'bz;
53 assign CON_A = 7'bz;
54 assign CON_B = 16'bz;
55 assign CON_C = 13'bz;
56 assign USB_PA0 = 1'bz;
57 assign USB_PA1 = 1'bz;
58 assign USB_PA3 = 1'bz;
59 assign USB_PA7 = 1'bz;
60 assign RAM_DQAP = 1'bz;
61 assign RAM_DQA = 8'bz;
62 assign RAM_DQBP = 1'bz;
63 assign RAM_DQB = 8'bz;
64
65
66 assign USB_PA2 = ~usb_rden;
67 assign USB_PA4 = usb_addr[0];
68 assign USB_PA5 = usb_addr[1];
69 assign USB_PA6 = ~usb_pktend;
70
71 reg [31:0] counter;
72 reg led_reg;
73// assign LED = counter[24];
74 assign LED = led_reg;
75
76 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
77 wire usb_fifo_aclr;
78 reg usb_fifo_tx_wrreq;
79 reg usb_fifo_rx_rdreq;
80 wire usb_fifo_tx_full, usb_fifo_rx_empty;
81 reg [7:0] usb_fifo_tx_data;
82 wire [7:0] usb_fifo_rx_data;
83 wire [1:0] usb_addr;
84
85 assign USB_SLRD = ~usb_rdreq;
86 assign USB_SLWR = ~usb_wrreq;
87
88 usb_fifo usb_fifo_unit
89 (
90 .usb_clk(USB_IFCLK),
91 .usb_data(USB_PB),
92 .usb_full(~USB_FLAGB),
93 .usb_empty(~USB_FLAGA),
94 .usb_wrreq(usb_wrreq),
95 .usb_rdreq(usb_rdreq),
96 .usb_rden(usb_rden),
97 .usb_pktend(usb_pktend),
98 .usb_addr(usb_addr),
99
100 .clk(CLK_50MHz),
101 .aclr(usb_fifo_aclr),
102
103 .tx_full(usb_fifo_tx_full),
104 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
105 .tx_data(usb_fifo_tx_data),
106
107 .rx_empty(usb_fifo_rx_empty),
108 .rx_rdreq(usb_fifo_rx_rdreq),
109 .rx_q(usb_fifo_rx_data)
110 );
111
112 reg [10:0] tst_counter;
113
114 reg [9:0] osc_counter;
115 reg osc_reset;
116 reg osc_byte_num;
117 wire [9:0] osc_start_addr;
118 reg [9:0] osc_addr;
119 wire [15:0] osc_q;
120
121 reg hst_reset;
122 reg [1:0] hst_byte_num;
123 reg [11:0] hst_addr;
124 wire [31:0] hst_q;
125
126 reg [3:0] state0, state1, state2;
127 reg adc_fifo_rdreq;
128 wire adc_fifo_rdempty;
129 reg adc_fifo_aclr;
130
131 reg [31:0] adc_counter;
132 reg adc_data_ready;
133 wire adc_clk;
134 reg [11:0] adc_data;
135 wire [11:0] raw_data;
136 wire [11:0] uwt_data;
137 wire [1:0] uwt_flag;
138
139 pll pll_unit(
140 .inclk0(CLK_50MHz),
141 .c0(adc_clk));
142
143 adc_fifo adc_fifo_unit (
144 .adc_clk(adc_clk),
145 .adc_data(adc_data),
146 .aclr(adc_fifo_aclr),
147 .rdclk(CLK_50MHz),
148 .rdreq(adc_fifo_rdreq),
149 .rdempty(adc_fifo_rdempty),
150 .raw_data(raw_data),
151 .uwt_data({uwt_flag, uwt_data}));
152
153 histogram histogram_unit (
154 .clk(CLK_50MHz),
155 .reset(hst_reset),
156 .data_ready(adc_data_ready),
157 .data(raw_data),
158 .address(hst_addr),
159 .q(hst_q)
160 );
161
162 oscilloscope oscilloscope_unit (
163 .clk(CLK_50MHz),
164 .reset(osc_reset),
165 .data_ready(adc_data_ready),
166 .raw_data(raw_data),
167 .uwt_data(uwt_data),
168 .threshold(16'd100),
169 .address(osc_addr),
170 .start_address(osc_start_addr),
171 .q(osc_q)
172 );
173
174/*
175 always @ (posedge adc_clk)
176 begin
177 counter <= counter + 32'd1;
178 end
179*/
180
181 always @ (posedge CLK_50MHz)
182 begin
183 case (state0)
184 1:
185 begin
186 if (~adc_fifo_rdempty)
187 begin
188// adc_counter <= adc_counter + 32'd1;
189 adc_fifo_rdreq <= 1'b1;
190 adc_data_ready <= 1'b1;
191 state0 <= 4'd2;
192 end
193 end
194
195 2:
196 begin
197 adc_fifo_rdreq <= 1'b0;
198 adc_data_ready <= 1'b0;
199 state0 <= 4'd1;
200 end
201
202 default:
203 begin
204 state0 <= 4'd1;
205 end
206 endcase
207 end
208
209 always @(posedge CLK_50MHz)
210 begin
211 case(state1)
212 1:
213 begin
214 usb_fifo_rx_rdreq <= 1'b0;
215 usb_fifo_tx_wrreq <= 1'b0;
216 hst_reset <= 1'b0;
217 osc_reset <= 1'b0;
218 state1 <= 4'd2;
219 end
220
221 2:
222 begin
223 usb_fifo_rx_rdreq <= ~usb_fifo_rx_empty;
224 if (~usb_fifo_rx_empty)
225 begin
226 case (usb_fifo_rx_data)
227 8'h30:
228 begin
229 hst_reset <= 1'b1;
230 state1 <= 4'd1;
231 end
232 8'h31:
233 begin
234 hst_addr <= 12'd0;
235 hst_byte_num <= 2'd0;
236 state1 <= 4'd3;
237 end
238 8'h32:
239 begin
240 led_reg <= 1'b1;
241 osc_reset <= 1'b1;
242 state1 <= 4'd1;
243 end
244 8'h33:
245 begin
246 led_reg <= 1'b0;
247 osc_addr <= osc_start_addr;
248 osc_counter <= 10'd0;
249 osc_byte_num <= 1'd0;
250 state1 <= 4'd6;
251 end
252 8'h34:
253 begin
254 led_reg <= 1'b1;
255 state1 <= 4'd1;
256 end
257 8'h35:
258 begin
259 led_reg <= 1'b0;
260 tst_counter <= 11'd0;
261 state1 <= 4'd9;
262 end
263 endcase
264 end
265 end
266
267 // hst transfer
268 3:
269 begin
270 usb_fifo_tx_data <= hst_q[7:0];
271 usb_fifo_tx_wrreq <= 1'b1;
272 hst_byte_num <= 2'd1;
273 state1 <= 4'd4;
274 end
275 4:
276 begin
277 if (~usb_fifo_tx_full)
278 begin
279 case (hst_byte_num)
280 2'd0: usb_fifo_tx_data <= hst_q[7:0];
281 2'd1: usb_fifo_tx_data <= hst_q[15:8];
282 2'd2: usb_fifo_tx_data <= hst_q[23:16];
283 2'd3: usb_fifo_tx_data <= hst_q[31:24];
284 endcase
285 if ((&hst_byte_num) & (&hst_addr))
286 begin
287 state1 <= 4'd5;
288 end
289 else
290 begin
291 if (&hst_byte_num)
292 begin
293 hst_addr <= hst_addr + 12'd1;
294 end
295 hst_byte_num <= hst_byte_num + 2'd1;
296 end
297 end
298 end
299 5:
300 begin
301 if (~usb_fifo_tx_full)
302 begin
303 usb_fifo_tx_wrreq <= 1'b0;
304 state1 <= 4'd1;
305 end
306 end
307
308 // osc transfer
309 6:
310 begin
311 usb_fifo_tx_data <= osc_q[7:0];
312 usb_fifo_tx_wrreq <= 1'b1;
313 osc_byte_num <= 1'd1;
314 state1 <= 4'd7;
315 end
316 7:
317 begin
318 if (~usb_fifo_tx_full)
319 begin
320 case (osc_byte_num)
321 1'd0: usb_fifo_tx_data <= osc_q[7:0];
322 1'd1: usb_fifo_tx_data <= osc_q[15:8];
323 endcase
324 if ((&osc_byte_num) & (&osc_counter))
325 begin
326 state1 <= 4'd8;
327 end
328 else
329 begin
330 if (&osc_byte_num)
331 begin
332 osc_addr <= osc_addr + 10'd1;
333 osc_counter <= osc_counter + 10'd1;
334 end
335 osc_byte_num <= osc_byte_num + 1'd1;
336 end
337 end
338 end
339 8:
340 begin
341 if (~usb_fifo_tx_full)
342 begin
343 usb_fifo_tx_wrreq <= 1'b0;
344 state1 <= 4'd1;
345 end
346 end
347 // tst transfer
348 9:
349 begin
350 usb_fifo_tx_data <= tst_counter;
351 usb_fifo_tx_wrreq <= 1'b1;
352 tst_counter <= tst_counter + 11'd1;
353 state1 <= 4'd10;
354 end
355 10:
356 begin
357 if (~usb_fifo_tx_full)
358 begin
359 usb_fifo_tx_data <= tst_counter;
360 if (tst_counter == 11'd0) //(&osc_counter)
361 begin
362 state1 <= 4'd11;
363 end
364 else
365 begin
366 tst_counter <= tst_counter + 11'd1;
367 end
368 end
369 end
370 11:
371 begin
372 if (~usb_fifo_tx_full)
373 begin
374 usb_fifo_tx_wrreq <= 1'b0;
375 state1 <= 4'd1;
376 end
377 end
378
379 default:
380 begin
381 state1 <= 4'd1;
382 end
383 endcase
384 end
385
386 always @ (posedge adc_clk)
387 begin
388 case (state2)
389 1:
390 begin
391 adc_data <= 12'd0;
392 state2 <= 4'd2;
393 end
394
395 2:
396 begin
397 adc_data <= 12'd1024;
398 state2 <= 4'd3;
399 end
400
401 3:
402 begin
403 adc_data <= 12'd2048;
404 state2 <= 4'd4;
405 end
406
407 4:
408 begin
409 adc_data <= 12'd3072;
410 state2 <= 4'd5;
411 end
412
413 5:
414 begin
415 adc_data <= 12'd4095;
416 state2 <= 4'd1;
417 end
418
419 default:
420 begin
421 state2 <= 4'd1;
422 end
423 endcase
424 end
425
426endmodule
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