source: trunk/3DEES/classifier.v@ 184

Last change on this file since 184 was 184, checked in by demin, 11 years ago

fix classifier
File size: 6.5 KB
Line 
1module classifier
2 #(
3 parameter width = 12 // bit width of the input data (unsigned)
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [18*width-1:0] cfg_data,
8 input wire [6*width-1:0] inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
9 input wire [5:0] inp_flag,
10 output wire [6:0] out_data,
11 output wire out_flag
12 );
13
14 reg out_flag_reg [2:0], out_flag_next [2:0];
15 reg [6:0] out_data_reg [2:0], out_data_next [2:0];
16 reg [5:0] inp_flag_reg, inp_flag_next;
17 reg [width-1:0] inp_data_reg [5:0], inp_data_next [5:0];
18 reg [15:0] int_pipe_reg [19:0], int_pipe_next [19:0];
19 reg [1:0] int_data_reg [3:0], int_data_next [3:0];
20 reg [4:0] int_temp_reg [1:0], int_temp_next [1:0];
21
22 wire [width-1:0] inp_data_wire [5:0];
23 wire [3:0] int_pipe_wire [5:0];
24 wire [15:0] int_comp_wire;
25
26 integer i;
27 genvar j;
28
29 generate
30 for (j = 0; j < 6; j = j + 1)
31 begin : CLASSIFIER_INPUT_DATA
32 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
33 end
34 endgenerate
35
36 generate
37 assign int_comp_wire[0] = inp_flag_reg[0] & (inp_data_reg[0] < cfg_data[width-1:0]);
38 assign int_comp_wire[1] = inp_flag_reg[0] & (inp_data_reg[0] > cfg_data[2*width-1:1*width]) & (inp_data_reg[0] < cfg_data[3*width-1:2*width]);
39
40 assign int_comp_wire[2] = inp_flag_reg[1] & (inp_data_reg[1] < cfg_data[4*width-1:3*width]);
41 assign int_comp_wire[3] = inp_flag_reg[1] & (inp_data_reg[1] > cfg_data[5*width-1:4*width]) & (inp_data_reg[1] < cfg_data[6*width-1:5*width]);
42
43 for (j = 0; j < 4; j = j + 1)
44 begin : CLASSIFIER_COMPARTORS
45 assign int_comp_wire[j*3+0+4] = (inp_data_reg[j+2] > cfg_data[(j*3+0+6)*width+width-1:(j*3+0+6)*width]);
46 assign int_comp_wire[j*3+1+4] = (inp_data_reg[j+2] > cfg_data[(j*3+1+6)*width+width-1:(j*3+1+6)*width]);
47 assign int_comp_wire[j*3+2+4] = (inp_data_reg[j+2] > cfg_data[(j*3+2+6)*width+width-1:(j*3+2+6)*width]);
48 end
49 endgenerate
50
51 generate
52 for (j = 0; j < 4; j = j + 1)
53 begin : CLASSIFIER_PIPELINE
54 assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
55 assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
56 assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
57 assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
58 assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
59 assign int_pipe_wire[j+2][3] = 1'b0;
60 end
61 endgenerate
62
63 always @(posedge clock)
64 begin
65 if (reset)
66 begin
67 inp_flag_reg <= {(6){1'b0}};
68 for (i = 0; i < 3; i = i + 1)
69 begin
70 out_data_reg[i] <= {(6){1'b0}};
71 out_flag_reg[i] <= 1'b0;
72 end
73 for (i = 0; i < 6; i = i + 1)
74 begin
75 inp_data_reg[i] <= {(width){1'b0}};
76 end
77 for (i = 0; i < 20; i = i + 1)
78 begin
79 int_pipe_reg[i] <= {(16){1'b0}};
80 end
81 for (i = 0; i < 4; i = i + 1)
82 begin
83 int_data_reg[i] <= {(2){1'b0}};
84 end
85 for (i = 0; i < 2; i = i + 1)
86 begin
87 int_temp_reg[i] <= {(5){1'b0}};
88 end
89 end
90 else
91 begin
92 inp_flag_reg <= inp_flag_next;
93 for (i = 0; i < 3; i = i + 1)
94 begin
95 out_data_reg[i] <= out_data_next[i];
96 out_flag_reg[i] <= out_flag_next[i];
97 end
98 for (i = 0; i < 6; i = i + 1)
99 begin
100 inp_data_reg[i] <= inp_data_next[i];
101 end
102 for (i = 0; i < 20; i = i + 1)
103 begin
104 int_pipe_reg[i] <= int_pipe_next[i];
105 end
106 for (i = 0; i < 4; i = i + 1)
107 begin
108 int_data_reg[i] <= int_data_next[i];
109 end
110 for (i = 0; i < 2; i = i + 1)
111 begin
112 int_temp_reg[i] <= int_temp_next[i];
113 end
114 end
115 end
116
117 always @*
118 begin
119 inp_flag_next = inp_flag_reg;
120 for (i = 0; i < 3; i = i + 1)
121 begin
122 out_data_next[i] = out_data_reg[i];
123 out_flag_next[i] = out_flag_reg[i];
124 end
125 for (i = 0; i < 6; i = i + 1)
126 begin
127 inp_data_next[i] = inp_data_reg[i];
128 end
129 for (i = 0; i < 20; i = i + 1)
130 begin
131 int_pipe_next[i] = int_pipe_reg[i];
132 end
133 for (i = 0; i < 4; i = i + 1)
134 begin
135 int_data_next[i] = int_data_reg[i];
136 end
137 for (i = 0; i < 2; i = i + 1)
138 begin
139 int_temp_next[i] = int_temp_reg[i];
140 end
141
142 if (frame)
143 begin
144 inp_flag_next = inp_flag;
145 for (i = 0; i < 6; i = i + 1)
146 begin
147 inp_data_next[i] = inp_data_wire[i];
148 end
149
150 if (out_flag_reg[2])
151 begin
152 for (i = 0; i < 3; i = i + 1)
153 begin
154 out_data_next[i] = {(6){1'b0}};
155 out_flag_next[i] = 1'b0;
156 end
157 for (i = 0; i < 20; i = i + 1)
158 begin
159 int_pipe_next[i] = {(16){1'b0}};
160 end
161 int_temp_next[0] = {(5){1'b0}};
162 int_temp_next[1] = {(5){1'b0}};
163 end
164 else
165 begin
166 out_data_next[0] = {(6){1'b0}};
167 out_data_next[1] = out_data_reg[0];
168 out_data_next[2] = out_data_reg[1];
169
170 out_flag_next[0] = 1'b1;
171 out_flag_next[1] = out_flag_reg[0];
172 out_flag_next[2] = out_flag_reg[1] & (out_data_reg[1] > out_data_reg[0]);
173
174 for (i = 0; i < 4; i = i + 1)
175 begin
176 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i]};
177 end
178 for (i = 4; i < 8; i = i + 1)
179 begin
180 int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag_reg[i-2]};
181 end
182 for (i = 8; i < 20; i = i + 1)
183 begin
184 int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-4]};
185 end
186
187 for (i = 0; i < 4; i = i + 1)
188 begin
189 case (int_pipe_wire[i+2][2:0])
190 3'b000: int_data_next[i] = 2'b00;
191 3'b001: int_data_next[i] = 2'b01;
192 3'b011: int_data_next[i] = 2'b10;
193 3'b111: int_data_next[i] = 2'b11;
194 default: int_data_next[i] = 2'd0;
195 endcase
196 end
197
198 int_temp_next[0] = {int_pipe_wire[1], ^int_pipe_wire[0]};
199 int_temp_next[1] = {1'b0, int_pipe_wire[0]};
200
201 case (int_temp_reg[0][4:0])
202 5'b00011: out_data_next[0][3:0] = {2'b00, int_data_next[0]};
203 5'b00111: out_data_next[0][3:0] = {2'b01, int_data_next[1]};
204 5'b01111: out_data_next[0][3:0] = {2'b10, int_data_next[2]};
205 5'b11111: out_data_next[0][3:0] = {2'b11, int_data_next[3]};
206 default: out_flag_next[0] = 1'b0;
207 endcase
208
209 case (int_temp_reg[1][3:0])
210 // S1_F, electron
211 4'b0001: out_data_next[0][6:4] = 3'b100;
212
213 // S1_F, proton
214 4'b0010: out_data_next[0][6:4] = 3'b101;
215
216 // S1_S, electron
217 4'b0100: out_data_next[0][6:4] = 3'b110;
218
219 // S1_S, proton
220 4'b1000: out_data_next[0][6:4] = 3'b111;
221
222 default: out_flag_next[0] = 1'b0;
223 endcase
224 end
225 end
226 end
227
228// assign out_data = {1'd0, int_pipe_wire[1+2][2:0], int_data_reg[1]};
229// assign out_data = {1'd0, int_comp_wire[0], int_temp_reg[1][3:0]};
230// assign out_data = {1'd0, int_temp_reg[0][4:0]};
231 assign out_data = out_data_reg[2];
232 assign out_flag = out_flag_reg[2];
233
234endmodule
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