source: sandbox/MultiChannelUSB/oscilloscope.v@ 187

Last change on this file since 187 was 157, checked in by demin, 13 years ago

remove workarounds for missed SRAM connections
File size: 5.3 KB
RevLine 
[27]1module oscilloscope
2 (
[90]3 input wire clock, frame, reset,
4
[96]5 input wire cfg_data,
[90]6
7 input wire trg_flag,
8
[103]9 input wire [63:0] osc_data,
[90]10
11 output wire ram_wren,
12 output wire [19:0] ram_addr,
13 inout wire [17:0] ram_data,
14
15 input wire bus_ssel, bus_wren,
16 input wire [19:0] bus_addr,
17 input wire [15:0] bus_mosi,
18
19 output wire [15:0] bus_miso,
20 output wire bus_busy
[27]21 );
22
23
[103]24 reg [63:0] osc_data_reg, osc_data_next;
[27]25
[90]26 reg [2:0] int_case_reg, int_case_next;
27
28 reg int_trig_reg, int_trig_next;
29 reg [19:0] int_trig_addr_reg, int_trig_addr_next;
30
[91]31 reg [19:0] int_cntr_reg [1:0];
32 reg [19:0] int_cntr_next [1:0];
33
[90]34 reg [15:0] bus_miso_reg, bus_miso_next;
35 reg bus_busy_reg, bus_busy_next;
36
37 reg ram_wren_reg [2:0];
38 reg ram_wren_next [2:0];
39
[96]40 reg [17:0] ram_data_reg [2:0];
41 reg [17:0] ram_data_next [2:0];
42
[90]43 reg [19:0] ram_addr_reg, ram_addr_next;
44
45 wire [17:0] ram_wren_wire;
46
47 assign ram_wren = ~ram_wren_reg[0];
48 assign ram_addr = ram_addr_reg;
49
50 integer i;
51 genvar j;
52
53 generate
54 for (j = 0; j < 18; j = j + 1)
55 begin : SRAM_WREN
56 assign ram_wren_wire[j] = ram_wren_reg[2];
[96]57 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
[90]58 end
59 endgenerate
60
61 always @(posedge clock)
[27]62 begin
63 if (reset)
[90]64 begin
[103]65 osc_data_reg <= 64'd0;
[90]66 ram_addr_reg <= 20'd0;
67 bus_miso_reg <= 16'd0;
68 bus_busy_reg <= 1'b0;
69 int_case_reg <= 5'd0;
[91]70 int_cntr_reg[0] <= 20'd0;
71 int_cntr_reg[1] <= 20'd0;
[90]72 int_trig_reg <= 1'b0;
73 int_trig_addr_reg <= 20'd0;
74
75 for(i = 0; i <= 2; i = i + 1)
76 begin
77 ram_wren_reg[i] <= 1'b0;
[96]78 ram_data_reg[i] <= 16'd0;
[90]79 end
[27]80 end
81 else
82 begin
[90]83 osc_data_reg <= osc_data_next;
84 ram_addr_reg <= ram_addr_next;
85 bus_miso_reg <= bus_miso_next;
86 bus_busy_reg <= bus_busy_next;
87 int_case_reg <= int_case_next;
[91]88 int_cntr_reg[0] <= int_cntr_next[0];
89 int_cntr_reg[1] <= int_cntr_next[1];
[90]90 int_trig_reg <= int_trig_next;
91 int_trig_addr_reg <= int_trig_addr_next;
92
93 for(i = 0; i <= 2; i = i + 1)
94 begin
95 ram_wren_reg[i] <= ram_wren_next[i];
[96]96 ram_data_reg[i] <= ram_data_next[i];
[90]97 end
[27]98 end
99 end
100
101 always @*
102 begin
103
[90]104 osc_data_next = osc_data_reg;
105 ram_addr_next = ram_addr_reg;
106 bus_miso_next = bus_miso_reg;
107 bus_busy_next = bus_busy_reg;
108 int_case_next = int_case_reg;
[91]109 int_cntr_next[0] = int_cntr_reg[0];
110 int_cntr_next[1] = int_cntr_reg[1];
[90]111 int_trig_next = int_trig_reg;
112 int_trig_addr_next = int_trig_addr_reg;
113
114 for(i = 0; i < 2; i = i + 1)
115 begin
116 ram_wren_next[i+1] = ram_wren_reg[i];
[96]117 ram_data_next[i+1] = ram_data_reg[i];
[90]118 end
119 ram_wren_next[0] = 1'b0;
[96]120 ram_data_next[0] = 18'd0;
[90]121
122 case (int_case_reg)
[51]123 0:
[27]124 begin
[90]125 bus_busy_next = 1'b0;
[91]126 int_cntr_next[0] = 20'd0;
127 int_cntr_next[1] = 20'd0;
[90]128 int_trig_next = 1'b0;
129
130 if (bus_ssel)
[27]131 begin
[157]132 bus_miso_next = ram_data[15:0];
[90]133 ram_wren_next[0] = bus_wren;
134 if (bus_wren)
135 begin
136 ram_addr_next = bus_addr;
[96]137 ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
[90]138 end
139 else
140 begin
[96]141 ram_addr_next = int_trig_addr_reg + bus_addr;
142// ram_addr_next = bus_addr;
[90]143 end
[27]144 end
[96]145 else if (cfg_data)
[27]146 begin
[90]147 // start recording
148 ram_wren_next[0] = 1'b1;
[96]149 ram_data_next[0] = 18'd0;
150 ram_addr_next = 20'd0;
[90]151 bus_busy_next = 1'b1;
152 int_case_next = 3'd1;
153 int_trig_addr_next = 20'd0;
[96]154// int_cntr_next[0] = {cfg_data[7:0], 10'd0};
155 int_cntr_next[0] = 20'd262143;
156// int_cntr_next[1] = {cfg_data[15:8], 10'd0};
157 int_cntr_next[1] = 20'd5000;
[27]158 end
[90]159
[27]160 end
[51]161
[96]162 // write zeros
[90]163 1:
[27]164 begin
[90]165 ram_wren_next[0] = 1'b1;
[96]166 ram_data_next[0] = 18'd2;
167 if(&ram_addr_reg)
168 begin
169 int_case_next = 3'd2;
170 end
171 else
172 begin
173 ram_addr_next = ram_addr_reg + 20'd1;
174 end
175 end
176
177 // sample recording
178 2:
179 begin
[90]180 if (frame)
[27]181 begin
[90]182 osc_data_next = osc_data;
183 ram_addr_next = ram_addr_reg + 20'd1;
[96]184 ram_wren_next[0] = 1'b1;
[157]185 ram_data_next[0] = {2'd0, osc_data[15:0]};
[96]186
187 int_case_next = 3'd3;
[51]188
[96]189 if (|int_cntr_reg[1])
[27]190 begin
[96]191 int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
192 int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
[27]193 end
[96]194 else if (int_trig_reg)
[51]195 begin
[96]196 if (|int_cntr_reg[0])
197 begin
198 int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
199 end
[51]200 end
[96]201 else if (trg_flag)
[91]202 begin
[96]203 int_trig_next = 1'b1;
204 int_trig_addr_next = ram_addr_reg - 20'd19999;
[91]205 end
[27]206 end
207 end
208
[96]209 3:
[27]210 begin
[96]211 ram_addr_next = ram_addr_reg + 20'd1;
[90]212 ram_wren_next[0] = 1'b1;
[157]213 ram_data_next[0] = {2'd0, osc_data_reg[31:16]};
[96]214 int_case_next = 3'd4;
[27]215 end
[90]216
[96]217 4:
[90]218 begin
[96]219 ram_addr_next = ram_addr_reg + 20'd1;
[90]220 ram_wren_next[0] = 1'b1;
[157]221 ram_data_next[0] = {2'd0, osc_data_reg[47:32]};
[96]222 int_case_next = 3'd5;
[90]223 end
224
[96]225 5:
[90]226 begin
[96]227 ram_addr_next = ram_addr_reg + 20'd1;
[90]228 ram_wren_next[0] = 1'b1;
[157]229 ram_data_next[0] = {2'd0, osc_data_reg[63:48]};
[96]230 if (|int_cntr_reg[0])
[90]231 begin
[96]232 int_case_next = 3'd2;
233 end
234 else
235 begin
[90]236 int_case_next = 3'd0;
237 end
238 end
239
[27]240 endcase
241 end
242
[90]243 assign bus_miso = bus_miso_reg;
244 assign bus_busy = bus_busy_reg;
[27]245
246endmodule
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