- Timestamp:
- Apr 15, 2014, 11:24:05 AM (11 years ago)
- Branches:
- ImprovedOutputFile, Timing, dual_readout, llp, master
- Children:
- f6b9fec
- Parents:
- b67be31
- Location:
- examples
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
examples/delphes_card_CMS_PileUp.tcl
rb67be31 rc526439 64 64 65 65 # pre-generated minbias input file 66 set PileUpFile ../../Delphes/MinBias.pileup66 set PileUpFile MinBias.pileup 67 67 68 68 # average expected pile up -
examples/delphes_card_CMS_PileUp_Hector.tcl
rb67be31 rc526439 67 67 68 68 # pre-generated minbias input file 69 set PileUpFile ../../Delphes/MinBias.pileup69 set PileUpFile MinBias.pileup 70 70 71 71 # average expected pile up
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