Changeset b65ca6b in git

Timestamp:

Jul 4, 2013, 2:41:42 AM (11 years ago)

Author:

pavel <pavel@…>

Branches:

ImprovedOutputFile, Timing, dual_readout, llp, master

Children:

ffaa11a

Parents:

b31dce0

Message:

add empty line after Pythia8 make rules

Files:

• Makefile (modified) (2 diffs)
• doc/genMakefile.tcl (modified) (3 diffs)

Makefile

@@ -916 +916 @@
         tmp/modules/PileUpMergerPythia8.$(ObjSuf)
 endif
+
 tmp/display/DelphesDisplay.$(ObjSuf): \
         display/DelphesDisplay.$(SrcSuf) \
@@ -930 +931 @@
         
 endif
+
 tmp/external/tcl/tclObj.$(ObjSuf): \
         external/tcl/tclObj.c

doc/genMakefile.tcl

@@ -93 +93 @@
     regsub {\.cc} $fileName {} srcName
     set srcObjName $prefix$srcName
-    
+
     if {$fileName == "modules/PileUpMergerPythia8.cc"} {
       lappend srcObjFilesPythia8 $srcObjName$objSuf
@@ -106 +106 @@
   puts [join $srcObjFiles $suffix]
   puts ""
-  
+
   puts {ifeq ($(HAS_PYTHIA8),true)}
   puts -nonewline "${srcPrefix}_OBJ += $suffix"
   puts [join $srcObjFilesPythia8 $suffix]
   puts {endif}
+  puts ""
 }
 
@@ -171 +172 @@
     puts ""
   }
-
 }