- Timestamp:
- May 4, 2018, 10:40:03 AM (6 years ago)
- Branches:
- ImprovedOutputFile, Timing, dual_readout, llp, master
- Children:
- a31331a
- Parents:
- 256a391 (diff), 0a122b5 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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cards/CMS_PhaseII/CMS_PhaseII_200PU_v03.tcl
r256a391 r622e3e8 133 133 134 134 # pre-generated minbias input file 135 #set PileUpFile /eos/cms/store/group/upgrade/delphes/PhaseII/MinBias_100k.pileup135 set PileUpFile /eos/cms/store/group/upgrade/delphes/PhaseII/MinBias_100k.pileup 136 136 #set PileUpFile MinBias.pileup 137 set PileUpFile MinBias_100k.pileup138 137 139 138 # average expected pile up
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