Timeline



Dec 21, 2009:

11:56 PM Changeset [87] by demin
fix writing of the last EPT sample to SRAM
11:55 PM Changeset [86] by demin
replace 3 ADC FIFO with one large FIFO
5:13 PM Changeset [85] by demin
add possibility to record full EPT information
5:09 PM Changeset [84] by demin
improve timings in all components

Nov 30, 2009:

12:51 PM Changeset [83] by demin
first working version
12:36 PM Changeset [82] by demin
several minor fixes
12:34 PM Changeset [81] by demin
activate all 3 ADC channels
12:38 AM Changeset [80] by demin
simplify analyser interface
12:36 AM Changeset [79] by demin
switch from 8 to 4 byte command
12:34 AM Changeset [78] by demin
make configuration frame always visible

Nov 29, 2009:

11:11 PM Changeset [77] by demin
add configuration form and activate all channels

Nov 28, 2009:

2:12 AM Changeset [76] by demin
add counter between peaks

Nov 26, 2009:

12:16 AM Changeset [75] by demin
fix osc_mux and trg_mux
12:15 AM Changeset [74] by demin
fix signal shape display configuration

Nov 25, 2009:

11:02 PM Changeset [73] by demin
first working version
11:02 PM Changeset [72] by demin
testing all components together
11:01 PM Changeset [71] by demin
move to central clock domain

Nov 23, 2009:

12:50 PM Changeset [70] by demin
intermediate working version with 32 bit histograms, test block and …

Nov 22, 2009:

11:16 PM Changeset [69] by demin
add I2C master
11:13 PM Changeset [68] by demin
add I2C master and switch from 24 to 32 bit histogram
11:12 PM Changeset [67] by demin
switch from 24 to 32 bit histogram
11:10 PM Changeset [66] by demin
first working version
Note: See TracTimeline for information about the timeline view.