Changeset 96
- Timestamp:
- Mar 12, 2010, 11:52:40 AM (14 years ago)
- File:
-
- 1 edited
-
trunk/MultiChannelUSB/oscilloscope.v (modified) (12 diffs)
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trunk/MultiChannelUSB/oscilloscope.v
r91 r96 3 3 input wire clock, frame, reset, 4 4 5 input wire [16:0]cfg_data,5 input wire cfg_data, 6 6 7 7 input wire trg_flag, … … 32 32 reg [19:0] int_cntr_next [1:0]; 33 33 34 reg [15:0] bus_mosi_reg [2:0];35 reg [15:0] bus_mosi_next [2:0];36 37 34 reg [15:0] bus_miso_reg, bus_miso_next; 38 35 reg bus_busy_reg, bus_busy_next; … … 41 38 reg ram_wren_next [2:0]; 42 39 43 reg [17:0] ram_data_reg, ram_data_next; 40 reg [17:0] ram_data_reg [2:0]; 41 reg [17:0] ram_data_next [2:0]; 42 44 43 reg [19:0] ram_addr_reg, ram_addr_next; 45 44 … … 56 55 begin : SRAM_WREN 57 56 assign ram_wren_wire[j] = ram_wren_reg[2]; 58 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[ j] : 1'bz;57 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz; 59 58 end 60 59 endgenerate … … 65 64 begin 66 65 osc_data_reg <= 48'd0; 67 ram_data_reg <= 18'd0;68 66 ram_addr_reg <= 20'd0; 69 67 bus_miso_reg <= 16'd0; … … 78 76 begin 79 77 ram_wren_reg[i] <= 1'b0; 80 bus_mosi_reg[i] <= 16'd0;78 ram_data_reg[i] <= 16'd0; 81 79 end 82 80 end … … 84 82 begin 85 83 osc_data_reg <= osc_data_next; 86 ram_data_reg <= ram_data_next;87 84 ram_addr_reg <= ram_addr_next; 88 85 bus_miso_reg <= bus_miso_next; … … 97 94 begin 98 95 ram_wren_reg[i] <= ram_wren_next[i]; 99 bus_mosi_reg[i] <= bus_mosi_next[i];96 ram_data_reg[i] <= ram_data_next[i]; 100 97 end 101 98 end … … 106 103 107 104 osc_data_next = osc_data_reg; 108 ram_data_next = ram_data_reg;109 105 ram_addr_next = ram_addr_reg; 110 106 bus_miso_next = bus_miso_reg; … … 119 115 begin 120 116 ram_wren_next[i+1] = ram_wren_reg[i]; 121 bus_mosi_next[i+1] = bus_mosi_reg[i];117 ram_data_next[i+1] = ram_data_reg[i]; 122 118 end 123 119 ram_wren_next[0] = 1'b0; 124 bus_mosi_next[0] = 16'd0;120 ram_data_next[0] = 18'd0; 125 121 126 122 case (int_case_reg) 127 123 0: 128 124 begin 129 ram_data_next = 18'd0;130 ram_addr_next = 20'd0;131 125 bus_busy_next = 1'b0; 132 126 int_cntr_next[0] = 20'd0; … … 134 128 int_trig_next = 1'b0; 135 129 136 ram_data_next = {bus_mosi_reg[1][15:8], 1'b0, bus_mosi_reg[1][7:0], 1'b0};137 138 130 if (bus_ssel) 139 131 begin … … 143 135 begin 144 136 ram_addr_next = bus_addr; 145 bus_mosi_next[0] = bus_mosi;137 ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0}; 146 138 end 147 139 else 148 140 begin 149 //ram_addr_next = int_trig_addr_reg + bus_addr;150 ram_addr_next = bus_addr;151 end 152 end 153 else if (cfg_data [16])141 ram_addr_next = int_trig_addr_reg + bus_addr; 142 // ram_addr_next = bus_addr; 143 end 144 end 145 else if (cfg_data) 154 146 begin 155 147 // start recording 156 148 ram_wren_next[0] = 1'b1; 149 ram_data_next[0] = 18'd0; 150 ram_addr_next = 20'd0; 157 151 bus_busy_next = 1'b1; 158 152 int_case_next = 3'd1; 159 153 int_trig_addr_next = 20'd0; 160 int_cntr_next[0] = {cfg_data[7:0], 10'd0}; 161 int_cntr_next[1] = {cfg_data[15:8], 10'd0}; 162 end 163 154 // int_cntr_next[0] = {cfg_data[7:0], 10'd0}; 155 int_cntr_next[0] = 20'd262143; 156 // int_cntr_next[1] = {cfg_data[15:8], 10'd0}; 157 int_cntr_next[1] = 20'd5000; 158 end 159 160 end 161 162 // write zeros 163 1: 164 begin 165 ram_wren_next[0] = 1'b1; 166 ram_data_next[0] = 18'd2; 167 if(&ram_addr_reg) 168 begin 169 int_case_next = 3'd2; 170 end 171 else 172 begin 173 ram_addr_next = ram_addr_reg + 20'd1; 174 end 164 175 end 165 176 166 177 // sample recording 167 1: 168 begin 169 ram_wren_next[0] = 1'b1; 178 2: 179 begin 170 180 if (frame) 171 181 begin 172 182 osc_data_next = osc_data; 173 183 ram_addr_next = ram_addr_reg + 20'd1; 184 ram_wren_next[0] = 1'b1; 185 ram_data_next[0] = {osc_data[15:8], 1'b0, osc_data[7:0], 1'b0}; 186 187 int_case_next = 3'd3; 188 189 if (|int_cntr_reg[1]) 190 begin 191 int_cntr_next[0] = int_cntr_reg[0] - 20'd1; 192 int_cntr_next[1] = int_cntr_reg[1] - 20'd1; 193 end 194 else if (int_trig_reg) 195 begin 196 if (|int_cntr_reg[0]) 197 begin 198 int_cntr_next[0] = int_cntr_reg[0] - 20'd1; 199 end 200 end 201 else if (trg_flag) 202 begin 203 int_trig_next = 1'b1; 204 int_trig_addr_next = ram_addr_reg - 20'd19999; 205 end 206 end 207 end 208 209 3: 210 begin 211 ram_addr_next = ram_addr_reg + 20'd1; 212 ram_wren_next[0] = 1'b1; 213 ram_data_next[0] = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0}; 214 int_case_next = 3'd4; 215 end 216 217 4: 218 begin 219 ram_addr_next = ram_addr_reg + 20'd1; 220 ram_wren_next[0] = 1'b1; 221 ram_data_next[0] = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0}; 222 int_case_next = 3'd5; 223 end 224 225 5: 226 begin 227 ram_addr_next = ram_addr_reg + 20'd1; 228 ram_wren_next[0] = 1'b1; 229 ram_data_next[0] = 18'd0; 230 if (|int_cntr_reg[0]) 231 begin 174 232 int_case_next = 3'd2; 175 176 if ((~int_trig_reg) & (trg_flag) & (int_cntr_reg[1] == 0)) 177 begin 178 int_trig_next = 1'b1; 179 int_trig_addr_next = ram_addr_reg; 180 end 181 182 if ((int_trig_reg) & (|int_cntr_reg[0])) 183 begin 184 int_cntr_next[0] = int_cntr_reg[0] - 20'd1; 185 end 186 187 if ((|int_cntr_reg[1])) 188 begin 189 int_cntr_next[1] = int_cntr_reg[1] - 20'd1; 190 end 191 end 192 end 193 194 2: 195 begin 196 ram_wren_next[0] = 1'b1; 197 ram_data_next = {osc_data_reg[15:8], 1'b0, osc_data_reg[7:0], 1'b0}; 198 ram_addr_next = ram_addr_reg + 20'd1; 199 int_case_next = 3'd3; 200 end 201 202 3: 203 begin 204 ram_wren_next[0] = 1'b1; 205 ram_data_next = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0}; 206 ram_addr_next = ram_addr_reg + 20'd1; 207 int_case_next = 3'd4; 208 end 209 210 4: 211 begin 212 ram_wren_next[0] = 1'b1; 213 ram_data_next = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0}; 214 int_case_next = 3'd1; 215 if (int_cntr_reg[0] == 0) 216 begin 217 ram_wren_next[0] = 1'b0; 218 ram_addr_next = 20'd0; 233 end 234 else 235 begin 219 236 int_case_next = 3'd0; 220 237 end
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