Changeset 58 for trunk


Ignore:
Timestamp:
Sep 18, 2009, 1:39:08 PM (15 years ago)
Author:
demin
Message:

code cleanup

Location:
trunk/MultiChannelUSB
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/MultiChannelUSB/Paella.qsf

    r56 r58  
    4848set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    4949set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
     50set_global_assignment -name MISC_FILE Paella.dpf
     51set_global_assignment -name VERILOG_FILE Paella.v
    5052set_global_assignment -name VERILOG_FILE adc_fifo.v
    5153set_global_assignment -name VERILOG_FILE adc_lvds.v
    5254set_global_assignment -name VERILOG_FILE adc_pll.v
     55set_global_assignment -name VERILOG_FILE control.v
    5356set_global_assignment -name VERILOG_FILE analyser.v
    5457set_global_assignment -name VERILOG_FILE histogram.v
    5558set_global_assignment -name VERILOG_FILE oscilloscope.v
    56 set_global_assignment -name VERILOG_FILE pll.v
    5759set_global_assignment -name VERILOG_FILE usb_fifo.v
    5860set_global_assignment -name VERILOG_FILE uwt_bior31.v
    59 set_global_assignment -name VERILOG_FILE Paella.v
    60 set_global_assignment -name MISC_FILE Paella.dpf
     61set_global_assignment -name VERILOG_FILE test.v
     62set_global_assignment -name VERILOG_FILE test_pll.v
    6163set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
    6264set_global_assignment -name ENABLE_CLOCK_LATENCY ON

  • trunk/MultiChannelUSB/adc_fifo.v

    r53 r58  
    44                input   wire    [11:0]  adc_data,
    55
    6                 input   wire                    aclr,
    7                 input   wire                    rdclk,
     6                input   wire                    clk,
    87
    98                output  wire                    ready,
    … …  
    6968                .use_eab("OFF"),
    7069                .write_aclr_synch("OFF")) fifo_raw (
    71                 .aclr(aclr),
     70                .aclr(1'b0),
    7271                .data(int_adc_data),
    73                 .rdclk(rdclk),
     72                .rdclk(clk),
    7473                .rdreq((~int_rdempty) & int_rdreq),
    7574                .wrclk(adc_clk),
    … …  
    9695                .use_eab("OFF"),
    9796                .write_aclr_synch("OFF")) fifo_uwt (
    98                 .aclr(aclr),
     97                .aclr(1'b0),
    9998                .data({uwt_flag3, uwt_peak3[11:0]}),
    100                 .rdclk(rdclk),
     99                .rdclk(clk),
    101100                .rdreq((~int_rdempty) & int_rdreq),
    102101                .wrclk(adc_clk),
    … …  
    110109                .wrusedw());
    111110
    112         always @ (posedge rdclk)
     111        always @(posedge clk)
    113112        begin
    114113                case (state)
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