source: trunk/MultiChannelUSB/adc_fifo.v@ 58

Last change on this file since 58 was 58, checked in by demin, 15 years ago

code cleanup
File size: 2.8 KB
Line 
1module adc_fifo
2 (
3 input wire adc_clk,
4 input wire [11:0] adc_data,
5
6 input wire clk,
7
8 output wire ready,
9 output wire [11:0] raw_data,
10 output wire [13:0] uwt_data
11 );
12
13 wire [31:0] uwt_d1, uwt_a1, uwt_peak1;
14 wire [31:0] uwt_d2, uwt_a2, uwt_peak2;
15 wire [31:0] uwt_d3, uwt_a3, uwt_peak3;
16 wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3;
17
18 wire [11:0] int_raw_q;
19 wire [13:0] int_uwt_q;
20
21 reg [11:0] int_raw_data;
22 reg [13:0] int_uwt_data;
23
24 wire [1:0] wrfull;
25
26 reg state;
27 reg int_rdreq, int_ready;
28 wire int_rdempty;
29
30 wire [11:0] int_adc_data;
31 assign int_adc_data = 12'hfff - adc_data;
32
33 uwt_bior31 #(.L(1)) uwt_1_unit (
34 .clk(adc_clk),
35 .x({20'h00000, int_adc_data}),
36 .d(uwt_d1),
37 .a(uwt_a1),
38 .peak(uwt_peak1),
39 .flag(uwt_flag1));
40
41 uwt_bior31 #(.L(2)) uwt_2_unit (
42 .clk(adc_clk),
43 .x(uwt_a1),
44 .d(uwt_d2),
45 .a(uwt_a2),
46 .peak(uwt_peak2),
47 .flag(uwt_flag2));
48
49 uwt_bior31 #(.L(3)) uwt_3_unit (
50 .clk(adc_clk),
51 .x(uwt_a2),
52 .d(uwt_d3),
53 .a(uwt_a3),
54 .peak(uwt_peak3),
55 .flag(uwt_flag3));
56
57 dcfifo #(
58 .intended_device_family("Cyclone III"),
59 .lpm_numwords(16),
60 .lpm_showahead("ON"),
61 .lpm_type("dcfifo"),
62 .lpm_width(12),
63 .lpm_widthu(4),
64 .rdsync_delaypipe(4),
65 .wrsync_delaypipe(4),
66 .overflow_checking("ON"),
67 .underflow_checking("ON"),
68 .use_eab("OFF"),
69 .write_aclr_synch("OFF")) fifo_raw (
70 .aclr(1'b0),
71 .data(int_adc_data),
72 .rdclk(clk),
73 .rdreq((~int_rdempty) & int_rdreq),
74 .wrclk(adc_clk),
75 .wrreq(~wrfull[0]),
76 .q(int_raw_q),
77 .rdempty(int_rdempty),
78 .wrfull(wrfull[0]),
79 .rdfull(),
80 .rdusedw(),
81 .wrempty(),
82 .wrusedw());
83
84 dcfifo #(
85 .intended_device_family("Cyclone III"),
86 .lpm_numwords(16),
87 .lpm_showahead("ON"),
88 .lpm_type("dcfifo"),
89 .lpm_width(14),
90 .lpm_widthu(4),
91 .rdsync_delaypipe(4),
92 .wrsync_delaypipe(4),
93 .overflow_checking("ON"),
94 .underflow_checking("ON"),
95 .use_eab("OFF"),
96 .write_aclr_synch("OFF")) fifo_uwt (
97 .aclr(1'b0),
98 .data({uwt_flag3, uwt_peak3[11:0]}),
99 .rdclk(clk),
100 .rdreq((~int_rdempty) & int_rdreq),
101 .wrclk(adc_clk),
102 .wrreq(~wrfull[1]),
103 .q(int_uwt_q),
104 .rdempty(),
105 .wrfull(wrfull[1]),
106 .rdfull(),
107 .rdusedw(),
108 .wrempty(),
109 .wrusedw());
110
111 always @(posedge clk)
112 begin
113 case (state)
114 1'b0:
115 begin
116 int_rdreq <= 1'b1;
117 int_ready <= 1'b0;
118 state <= 1'b1;
119 end
120
121 1'b1:
122 begin
123 if (~int_rdempty)
124 begin
125 int_raw_data <= int_raw_q;
126 int_uwt_data <= int_uwt_q;
127 int_rdreq <= 1'b0;
128 int_ready <= 1'b1;
129 state <= 1'b0;
130 end
131 end
132
133 default:
134 begin
135 int_rdreq <= 1'b1;
136 int_ready <= 1'b0;
137 state <= 1'b1;
138 end
139 endcase
140 end
141
142 assign ready = int_ready;
143 assign raw_data = int_raw_data;
144 assign uwt_data = int_uwt_data;
145
146endmodule
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