- Timestamp:
- Sep 17, 2009, 6:35:11 PM (15 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/Paella.v
r50 r54 143 143 assign adc_clk[1] = ADC_FCO; 144 144 assign adc_clk[2] = ADC_FCO; 145 /*145 146 146 assign adc_clk[3] = CON_B[0]; 147 147 assign adc_data[3] = CON_B[12:1]; 148 */ 148 149 wire adc_pll_clk; 150 149 151 wire tst_adc_clk; 150 152 reg [11:0] tst_adc_data; 151 153 /* 152 154 assign adc_clk[3] = tst_adc_clk; 153 155 assign adc_data[3] = tst_adc_data; 156 */ 157 /* 158 adc_pll adc_pll_unit( 159 .inclk0(ADC_FCO), 160 .c0(adc_pll_clk)); 161 */ 154 162 155 163 pll pll_unit( … … 170 178 .sdoin()); 171 179 */ 180 172 181 adc_lvds adc_lvds_unit ( 173 182 .lvds_dco(ADC_DCO), 183 // .lvds_dco(adc_pll_clk), 174 184 .lvds_fco(ADC_FCO), 175 185 .lvds_d(ADC_D), … … 180 190 genvar i; 181 191 generate 182 for (i = 2; i < 4; i = i + 1)192 for (i = 0; i < 4; i = i + 1) 183 193 begin : MCA_CHAIN 184 194 adc_fifo adc_fifo_unit ( … … 197 207 .uwt_flag(uwt_flag[i]), 198 208 .uwt_data(uwt_data[i]), 199 .threshold(12'd 5),209 .threshold(12'd10), 200 210 .peak_ready(ana_peak_ready[i]), 201 211 .peak(ana_peak[i])); 202 /* 212 203 213 histogram histogram_unit ( 204 214 .clk(CLK_50MHz), 205 215 .reset(hst_reset[i]), 206 216 .data_ready(adc_data_ready[i]), 207 .data(raw_data[i]), 217 // .data(raw_data[i]), 218 .data(uwt_data[i]), 208 219 .address(hst_addr[i]), 209 220 .q(hst_q[i])); 210 */ 221 /* 211 222 histogram histogram_unit ( 212 223 .clk(CLK_50MHz), … … 216 227 .address(hst_addr[i]), 217 228 .q(hst_q[i])); 218 229 */ 219 230 oscilloscope oscilloscope_unit ( 220 231 .clk(CLK_50MHz), … … 223 234 .raw_data(raw_data[i]), 224 235 .uwt_data(uwt_data[i]), 225 .threshold(16'd 100),236 .threshold(16'd40), 226 237 .address(osc_addr[i]), 227 238 .start_address(osc_start_addr[i]), … … 341 352 usb_fifo_rx_rdreq <= 1'b0; 342 353 tst_counter <= 11'd0; 343 state1 <= 4'd 9;354 state1 <= 4'd6; 344 355 end 345 356 endcase … … 354 365 state1 <= 4'd4; 355 366 end 367 356 368 4: 357 369 begin 358 usb_fifo_tx_data <= mux_q; 359 usb_fifo_tx_wrreq <= 1'b1; 360 mux_byte <= 2'd1; 370 usb_fifo_tx_wrreq <= 1'b0; 361 371 state1 <= 4'd5; 362 372 end 373 363 374 5: 364 375 begin … … 366 377 begin 367 378 usb_fifo_tx_data <= mux_q; 379 usb_fifo_tx_wrreq <= 1'b1; 368 380 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr)) 369 381 begin 370 state1 <= 4'd 6;382 state1 <= 4'd1; 371 383 end 372 384 else 373 385 begin 386 state1 <= 4'd4; 374 387 if (mux_byte == mux_max_byte) 375 388 begin … … 384 397 end 385 398 end 399 400 // tst transfer 386 401 6: 387 begin388 if (~usb_fifo_tx_full)389 begin390 usb_fifo_tx_wrreq <= 1'b0;391 state1 <= 4'd1;392 end393 end394 // tst transfer395 7:396 402 begin 397 403 usb_fifo_tx_data <= tst_counter; … … 400 406 state1 <= 4'd8; 401 407 end 402 8:408 7: 403 409 begin 404 410 if (~usb_fifo_tx_full) … … 415 421 end 416 422 end 417 9:423 8: 418 424 begin 419 425 if (~usb_fifo_tx_full)
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