Changeset 42 for trunk/MultiChannelUSB/adc_lvds.v
- Timestamp:
- Sep 12, 2009, 2:04:57 AM (16 years ago)
- File:
-
- 1 edited
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trunk/MultiChannelUSB/adc_lvds.v
r41 r42 5 5 input wire [2:0] lvds_d, 6 6 7 output wire adc_clk, 8 output wire [11:0] adc_db, 9 output wire [11:0] adc_dc, 10 output wire [11:0] adc_dd 7 output reg [11:0] adc_db, 8 output reg [11:0] adc_dc, 9 output reg [11:0] adc_dd 11 10 ); 12 11 13 12 14 13 wire [2:0] int_data_h, int_data_l; 15 reg [11:0] int_data_ sr[2:0];14 reg [11:0] int_data_next [2:0]; 16 15 reg [11:0] int_data [2:0]; 17 reg int_fco;18 19 integer i;20 16 21 17 altddio_in #( 22 18 .intended_device_family("Cyclone III"), 23 .invert_input_clocks("O FF"),19 .invert_input_clocks("ON"), 24 20 .lpm_type("altddio_in"), 25 21 .width(3)) altddio_in_unit ( … … 36 32 always @ (posedge lvds_dco) 37 33 begin 38 for(i = 0; i < 3; i = i + 1) 39 begin 40 int_data_sr[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]}; 41 end 42 43 // one clock delay for FCO 44 int_fco <= lvds_fco; 45 46 if((lvds_fco) & (~int_fco)) 47 begin 48 for(i = 0; i < 3; i = i + 1) 49 begin 50 int_data[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]}; 51 end 52 end 34 int_data[0] <= int_data_next[0]; 35 int_data[1] <= int_data_next[1]; 36 int_data[2] <= int_data_next[2]; 53 37 end 54 38 55 assign adc_clk = int_fco; 56 assign adc_db = int_data[0]; 57 assign adc_dc = int_data[1]; 58 assign adc_dd = int_data[2]; 39 always @ (posedge lvds_fco) 40 begin 41 adc_db <= int_data_next[0]; 42 adc_dc <= int_data_next[1]; 43 adc_dd <= int_data_next[2]; 44 end 45 46 always @* 47 begin 48 int_data_next[0] = {int_data[0][9:0], int_data_l[0], int_data_h[0]}; 49 int_data_next[1] = {int_data[1][9:0], int_data_l[1], int_data_h[1]}; 50 int_data_next[2] = {int_data[2][9:0], int_data_l[2], int_data_h[2]}; 51 end 59 52 60 53 endmodule
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