Changeset 180 for trunk/3DEES/Paella.v
- Timestamp:
- Jan 15, 2014, 1:30:27 AM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/Paella.v
r178 r180 7 7 input wire ADC_FCO, 8 8 input wire [5:0] ADC_D, 9 10 output wire [3:0] PWM,11 12 output wire [1:0] SPI_SEL,13 output wire SPI_SDO,14 output wire SPI_CLK,15 output wire ADC_RST,16 9 17 10 output wire USB_SLRD, … … 43 36 assign RAM_ADDR = 20'h00000; 44 37 */ 45 assign ADC_RST = 1'b0;46 38 47 39 assign RAM_CLK = sys_clock; … … 101 93 wire [12:0] amp_data [3*N-1:0]; 102 94 95 wire cls_flag; 96 wire [5:0] cls_data; 97 103 98 wire [1:0] amp_mux_flag [2:0]; 104 99 wire [11:0] amp_mux_data [2:0]; … … 125 120 wire i2c_reset; 126 121 127 assign tmp_data = 12' h000;122 assign tmp_data = 12'd0; 128 123 assign sys_clock = CLK_100MHz; 129 124 /* … … 167 162 wire cfg_reset; 168 163 169 wire [ 12:0] bus_ssel;164 wire [2:0] bus_ssel; 170 165 wire bus_wren; 171 166 wire [31:0] bus_addr; 172 167 wire [15:0] bus_mosi; 173 wire [15:0] bus_miso [ 10:0];174 wire [ 12:0] bus_busy;168 wire [15:0] bus_miso [2:0]; 169 wire [2:0] bus_busy; 175 170 176 171 wire [15:0] mrg_bus_miso; 177 172 wire mrg_bus_busy; 178 173 179 wire [ 11*16-1:0] int_bus_miso;174 wire [3*16-1:0] int_bus_miso; 180 175 181 176 genvar j; … … 203 198 begin : MUX_DATA 204 199 assign int_mux_data[j] = { 205 {4'd0, amp_flag[j][0], 7'd0}, 200 {6'd0, cls_data}, 201 {4'd0, cls_flag, 7'd0}, 202 // {4'd0, amp_flag[j][0], 7'd0}, 206 203 amp_data[j][11:0], 207 clp_data[j][11:0], 208 sys_data[j]}; 204 clp_data[j][11:0] 205 // sys_data[j] 206 }; 209 207 end 210 208 endgenerate … … 288 286 begin : DECONV_CHAIN 289 287 290 clip #(.shift(2 2), .width(19), .widthr(12)) clip_unit (288 clip #(.shift(21), .width(19), .widthr(13)) clip_unit ( 291 289 .clock(sys_clock), 292 290 .frame(sys_frame), 293 291 .reset(1'b0), 294 292 .del_data({6'd0, 6'd32, 6'd32, 6'd32}), 295 // .del_data({6'd0, cfg_bits[3 7+6*j][5:0], cfg_bits[35+6*j][5:0], cfg_bits[33+6*j][5:0]}),293 // .del_data({6'd0, cfg_bits[35+6*j][5:0], cfg_bits[33+6*j][5:0], cfg_bits[31+6*j][5:0]}), 296 294 .amp_data({6'd0, 6'd20, 6'd20, 6'd20}), 297 295 .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}), 298 296 // exp(-32/1000)*1024*20 299 // .tau_data({16'd0, cfg_bits[3 6+6*j], cfg_bits[34+6*j], cfg_bits[32+6*j]}),297 // .tau_data({16'd0, cfg_bits[33+6*j], cfg_bits[32+6*j], cfg_bits[30+6*j]}), 300 298 .inp_data({ 301 299 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}), … … 324 322 .frame(sys_frame), 325 323 .reset(1'b0), 326 .min_data( {1'b0, cfg_bits[7][11:0]}),324 .min_data(13'd20), 327 325 .max_data(13'd4095), 328 // .cfg_data(cfg_bits[6+2*j][11:0]),329 326 .inp_data(clp_data[j]), 330 327 .out_flag(amp_flag[j]), … … 333 330 endgenerate 334 331 332 // {D3, D2, D1, S2, S1_S, S1_F} 333 classifier #(.width(12)) classifier_unit ( 334 .clock(sys_clock), 335 .frame(sys_frame), 336 .reset(1'b0), 337 .cfg_data({12'd20, 12'd20, 338 12'd20, 12'd20, 12'd20, 12'd20, 12'd2000, 12'd20, 339 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}), 340 .inp_data({amp_data[5][11:0], amp_data[4][11:0], amp_data[0][11:0], 341 amp_data[0][11:0], amp_data[1][11:0], amp_data[0][11:0]}), 342 .inp_flag({amp_flag[5][0], amp_flag[4][0], amp_flag[0][0], 343 amp_flag[0][0], amp_flag[1][0], amp_flag[0][0]}), 344 .out_flag(cls_flag), 345 .out_data(cls_data)); 346 335 347 histogram32 histogram32_unit ( 336 348 .clock(sys_clock), 337 349 .frame(sys_frame), 338 350 .reset(cfg_bits[0][5]), 339 .hst_good( (amp_flag[0][1]) & (cnt_good[0]) & (cfg_bits[13][1])),340 .hst_data( amp_data[0]),351 .hst_good(cls_flag & cfg_bits[6][0]), 352 .hst_data(cls_data), 341 353 .bus_ssel(bus_ssel[2]), 342 354 .bus_wren(bus_wren), 343 .bus_addr(bus_addr[ 12:0]),355 .bus_addr(bus_addr[6:0]), 344 356 .bus_mosi(bus_mosi), 345 357 .bus_miso(bus_miso[2]), 346 358 .bus_busy(bus_busy[2])); 347 359 348 counter hst_counter_unit ( 349 .clock(sys_clock), 350 .frame((sys_frame) & (~amp_flag[0][1])), 351 // .frame(sys_frame), 352 .reset(cfg_bits[0][8]), 353 .setup(cfg_bits[13][0]), 354 .count(cfg_bits[13][1]), 355 .bus_ssel(bus_ssel[5]), 356 .bus_wren(bus_wren), 357 .bus_addr(bus_addr[1:0]), 358 .bus_mosi(bus_mosi), 359 .bus_miso(bus_miso[5]), 360 .bus_busy(bus_busy[5]), 361 .cnt_good(cnt_good[0])); 362 363 364 i2c_fifo i2c_unit( 365 .clock(sys_clock), 366 .reset(i2c_reset), 367 /* 368 normal connection 369 .i2c_sda(I2C_SDA), 370 .i2c_scl(I2C_SCL), 371 372 following is a cross wire connection for EPT 373 */ 374 .i2c_sda(I2C_SCL), 375 .i2c_scl(I2C_SDA), 376 377 .bus_ssel(bus_ssel[11]), 378 .bus_wren(bus_wren), 379 .bus_mosi(bus_mosi), 380 .bus_busy(bus_busy[11])); 381 382 spi_fifo spi_unit( 383 .clock(sys_clock), 384 .reset(1'b0), 385 .spi_sel(SPI_SEL), 386 .spi_sdo(SPI_SDO), 387 .spi_clk(SPI_CLK), 388 389 .bus_ssel(bus_ssel[12]), 390 .bus_wren(bus_wren), 391 .bus_mosi(bus_mosi), 392 .bus_busy(bus_busy[12])); 393 394 pwm pwm_unit( 395 .clock(sys_clock), 396 .cfg_data({cfg_bits[31], cfg_bits[30], cfg_bits[29]}), 397 .out_data(PWM)); 398 399 generate 400 for (j = 0; j < 11; j = j + 1) 360 361 generate 362 for (j = 0; j < 3; j = j + 1) 401 363 begin : BUS_OUTPUT 402 364 assign int_bus_miso[j*16+15:j*16] = bus_miso[j]; … … 405 367 406 368 lpm_mux #( 407 .lpm_size( 11),369 .lpm_size(3), 408 370 .lpm_type("LPM_MUX"), 409 371 .lpm_width(16), 410 .lpm_widths( 4)) bus_miso_mux_unit (411 .sel(bus_addr[ 31:28]),372 .lpm_widths(2)) bus_miso_mux_unit ( 373 .sel(bus_addr[29:28]), 412 374 .data(int_bus_miso), 413 375 .result(mrg_bus_miso)); 414 376 415 377 lpm_mux #( 416 .lpm_size( 13),378 .lpm_size(3), 417 379 .lpm_type("LPM_MUX"), 418 380 .lpm_width(1), 419 .lpm_widths( 4)) bus_busy_mux_unit (420 .sel(bus_addr[ 31:28]),381 .lpm_widths(2)) bus_busy_mux_unit ( 382 .sel(bus_addr[29:28]), 421 383 .data(bus_busy), 422 384 .result(mrg_bus_busy)); 423 385 424 386 lpm_decode #( 425 .lpm_decodes( 13),387 .lpm_decodes(3), 426 388 .lpm_type("LPM_DECODE"), 427 .lpm_width( 4)) lpm_decode_unit (428 .data(bus_addr[ 31:28]),389 .lpm_width(2)) lpm_decode_unit ( 390 .data(bus_addr[29:28]), 429 391 .eq(bus_ssel)); 430 392
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