Changeset 178 for trunk/3DEES/clip.v

Timestamp:

Dec 20, 2013, 10:10:03 AM (11 years ago)

Author:

demin

Message:

adapt to 6ch

File:

• trunk/3DEES/clip.v (modified) (15 diffs)

trunk/3DEES/clip.v

@@ -31 +31 @@
         wire    [widthr-1:0]    out_data_wire;
 
+        reg             [width3-1:0]    add_data_reg [4:0], add_data_next [4:0];
         wire    [width3-1:0]    add_data_wire;
 
@@ -104 +105 @@
                 - {2'b0, mul_data_wire1};
 
-        assign out_data_wire = add_data_wire[width3-1] ? {(widthr){1'b0}} :
-                  add_data_wire[shift+widthr-1:shift]
-                + {{(widthr-1){add_data_wire[width3-1]}}, add_data_wire[shift-1]};
+        assign out_data_wire = add_data_reg[0][width3-1] ? {(widthr){1'b0}} :
+                  add_data_reg[0][shift+widthr-1:shift]
+                + {{(widthr-1){add_data_reg[0][width3-1]}}, add_data_reg[0][shift-1]};
 
 
@@ -172 +173 @@
                         begin
                                 out_data_reg[i] <= {(widthr){1'b0}};
+                                add_data_reg[i] <= {(width3){1'b0}};
                         end
                 end
@@ -191 +193 @@
                         begin
                                 out_data_reg[i] <= out_data_next[i];
+                                add_data_reg[i] <= add_data_next[i];
                         end                  
                 end             
@@ -212 +215 @@
                 begin
                         out_data_next[i] = out_data_reg[i];
+                        add_data_next[i] = add_data_reg[i];
                 end                  
 
@@ -230 +234 @@
                                 begin
                                         out_data_next[i] = {(widthr){1'b0}};
+                                        add_data_next[i] = {(width3){1'b0}};
                                 end                  
 
@@ -264 +269 @@
                                         // prepare registers for 1st sum                                        
                                         inp_data_next[0] = inp_data_wire[0];
+                                        // prepare registers for 2nd shift                                      
+                                        add_data_next[0] = add_data_reg[2];
 
                                         tau_data_next = tau_data_wire[0];
@@ -274 +281 @@
                                         int_addr_next[5:0] = del_addr_reg;
                                         // register 1st product
-                                        out_data_next[0] = out_data_wire;
+                                        add_data_next[1] = add_data_wire;
+                                        out_data_next[1] = out_data_wire;
                                 end
                         end
@@ -286 +294 @@
                                 // prepare registers for 2nd sum
                                 inp_data_next[0] = inp_data_reg[1];
+                                // prepare registers for 3rd shift
+                                add_data_next[0] = add_data_reg[3];
                                 
                                 tau_data_next = tau_data_wire[1];
@@ -291 +301 @@
 
                                 // register 2nd product
-                                out_data_next[1] = out_data_wire;
+                                add_data_next[2] = add_data_wire;
+                                out_data_next[2] = out_data_wire;
 
                                 int_case_next = 3'd4;
@@ -304 +315 @@
                                 // prepare registers for 3rd sum        
                                 inp_data_next[0] = inp_data_reg[2];
+                                // prepare registers for 4th shift      
+                                add_data_next[0] = add_data_reg[4];
 
                                 tau_data_next = tau_data_wire[2];
@@ -309 +322 @@
                                 
                                 // register 3rd product
-                                out_data_next[2] = out_data_wire;
+                                add_data_next[3] = add_data_wire;
+                                out_data_next[3] = out_data_wire;
                                 
                                 del_addr_next = del_addr_reg + 6'd1;
@@ -326 +340 @@
                                 // prepare registers for 4th sum        
                                 inp_data_next[0] = inp_data_reg[3];
+                                // prepare registers for 1st shift      
+                                add_data_next[0] = add_data_reg[1];
 
                                 tau_data_next = tau_data_wire[3];
@@ -331 +347 @@
                                 
                                 // register 4th product
-                                out_data_next[3] = out_data_wire;
+                                add_data_next[4] = add_data_wire;
+                                out_data_next[4] = out_data_wire;
                                              
                                 // register 4th output
-                                out_data_next[4] = out_data_reg[0];
+                                out_data_next[0] = out_data_reg[1];
 
                                 int_case_next = 3'd2;
@@ -345 +362 @@
         end
 
-        assign out_data = {out_data_reg[3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};
+        assign out_data = {out_data_reg[4], out_data_reg[3], out_data_reg[2], out_data_reg[0]};
 
 endmodule