Changeset 178 for trunk/3DEES/clip.v
- Timestamp:
- Dec 20, 2013, 10:10:03 AM (11 years ago)
- File:
-
- 1 edited
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trunk/3DEES/clip.v
r154 r178 31 31 wire [widthr-1:0] out_data_wire; 32 32 33 reg [width3-1:0] add_data_reg [4:0], add_data_next [4:0]; 33 34 wire [width3-1:0] add_data_wire; 34 35 … … 104 105 - {2'b0, mul_data_wire1}; 105 106 106 assign out_data_wire = add_data_ wire[width3-1] ? {(widthr){1'b0}} :107 add_data_ wire[shift+widthr-1:shift]108 + {{(widthr-1){add_data_ wire[width3-1]}}, add_data_wire[shift-1]};107 assign out_data_wire = add_data_reg[0][width3-1] ? {(widthr){1'b0}} : 108 add_data_reg[0][shift+widthr-1:shift] 109 + {{(widthr-1){add_data_reg[0][width3-1]}}, add_data_reg[0][shift-1]}; 109 110 110 111 … … 172 173 begin 173 174 out_data_reg[i] <= {(widthr){1'b0}}; 175 add_data_reg[i] <= {(width3){1'b0}}; 174 176 end 175 177 end … … 191 193 begin 192 194 out_data_reg[i] <= out_data_next[i]; 195 add_data_reg[i] <= add_data_next[i]; 193 196 end 194 197 end … … 212 215 begin 213 216 out_data_next[i] = out_data_reg[i]; 217 add_data_next[i] = add_data_reg[i]; 214 218 end 215 219 … … 230 234 begin 231 235 out_data_next[i] = {(widthr){1'b0}}; 236 add_data_next[i] = {(width3){1'b0}}; 232 237 end 233 238 … … 264 269 // prepare registers for 1st sum 265 270 inp_data_next[0] = inp_data_wire[0]; 271 // prepare registers for 2nd shift 272 add_data_next[0] = add_data_reg[2]; 266 273 267 274 tau_data_next = tau_data_wire[0]; … … 274 281 int_addr_next[5:0] = del_addr_reg; 275 282 // register 1st product 276 out_data_next[0] = out_data_wire; 283 add_data_next[1] = add_data_wire; 284 out_data_next[1] = out_data_wire; 277 285 end 278 286 end … … 286 294 // prepare registers for 2nd sum 287 295 inp_data_next[0] = inp_data_reg[1]; 296 // prepare registers for 3rd shift 297 add_data_next[0] = add_data_reg[3]; 288 298 289 299 tau_data_next = tau_data_wire[1]; … … 291 301 292 302 // register 2nd product 293 out_data_next[1] = out_data_wire; 303 add_data_next[2] = add_data_wire; 304 out_data_next[2] = out_data_wire; 294 305 295 306 int_case_next = 3'd4; … … 304 315 // prepare registers for 3rd sum 305 316 inp_data_next[0] = inp_data_reg[2]; 317 // prepare registers for 4th shift 318 add_data_next[0] = add_data_reg[4]; 306 319 307 320 tau_data_next = tau_data_wire[2]; … … 309 322 310 323 // register 3rd product 311 out_data_next[2] = out_data_wire; 324 add_data_next[3] = add_data_wire; 325 out_data_next[3] = out_data_wire; 312 326 313 327 del_addr_next = del_addr_reg + 6'd1; … … 326 340 // prepare registers for 4th sum 327 341 inp_data_next[0] = inp_data_reg[3]; 342 // prepare registers for 1st shift 343 add_data_next[0] = add_data_reg[1]; 328 344 329 345 tau_data_next = tau_data_wire[3]; … … 331 347 332 348 // register 4th product 333 out_data_next[3] = out_data_wire; 349 add_data_next[4] = add_data_wire; 350 out_data_next[4] = out_data_wire; 334 351 335 352 // register 4th output 336 out_data_next[ 4] = out_data_reg[0];353 out_data_next[0] = out_data_reg[1]; 337 354 338 355 int_case_next = 3'd2; … … 345 362 end 346 363 347 assign out_data = {out_data_reg[ 3], out_data_reg[2], out_data_reg[1], out_data_reg[4]};364 assign out_data = {out_data_reg[4], out_data_reg[3], out_data_reg[2], out_data_reg[0]}; 348 365 349 366 endmodule
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