Changeset 178 for trunk/3DEES/adc_lvds.v

Timestamp:

Dec 20, 2013, 10:10:03 AM (11 years ago)

Author:

demin

Message:

adapt to 6ch

File:

• trunk/3DEES/adc_lvds.v (modified) (4 diffs)

trunk/3DEES/adc_lvds.v

@@ -4 +4 @@
 module adc_lvds
         #(
-                parameter       size    =       8, // number of channels
-                parameter       width   =       24 // channel resolution
+                parameter       size    =       3, // number of channels
+                parameter       width   =       12 // channel resolution
         )
         (
@@ -13 +13 @@
                 input   wire                                            lvds_fco,
                 input   wire    [size-1:0]                      lvds_d,
+                input   wire    [11:0]              test,
 
                 output  wire                                            adc_frame,
@@ -20 +21 @@
         localparam      width2  =       width + 2;
                 
+
         reg                                                     state, int_rdreq, adc_frame_reg;
         wire                                            int_wrfull, int_rdempty;
@@ -47 +49 @@
 // LSB first
 //                      assign int_data_wire[j*width+width-1:j*width] = {int_data_n[j], int_data_p[j], int_data_reg[j*width+width-1:j*width+2]};
-                        assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
-                        assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
+
+//                      assign int_fifo_wire[j*width+width-1:j*width] = test;
+
+                        assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_reg[j*width2+width2-3:j*width2], int_data_p[j], int_data_n[j]};
+                        assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+2];
+//                      assign int_fifo_wire[j*width+width-1:j*width] = int_data_reg[j*width2+width2-1:j*width2+8];
+
+//                      assign int_data_wire[j*width2+width2-1:j*width2] = {int_data_n[j], int_data_p[j], int_data_reg[j*width2+width2-1:j*width2+2]};
+//                      assign [j*width+width-1:j*width] = int_data_reg[j*width2+width2-3:j*width2];
                 end
         endgenerate
+
 
         dcfifo #(